Unused Bits 31 : 8
PTE Bit 7
R/W
0x0
The sending of TX_REQ.
In DMA1 mode (FIFO on), if PTE is set to 1, when TFL is less than trig, send the DMA request.
If PTE is set to 0, when FIFO is empty, send the DMA request.
The DMA request will stop when FIFO is full.
In DMA0 mode, if PTE is set to 1 and FIFO is on, when TFL is less than trig, send DMA request.
If PTE is set to 1 and FIFO is off, when THRE is empty, send DMA request.
If PTE is set to 0, when FIFO is empty, send DMA request.
DMA_PTE_RX Bit 6
R/W
0x0
The sending of RX_DRQ.
In DMA1 mode, when RFL is more than or equal to trig or receive timeout, send DRQ.
In DMA0 mode, if DMA_PTE_RX is 1 and FIFO is on, when RFL is more than trig, send DRQ.
In other cases, once the receive data is valid, send DRQ.
SIR_RX_INVERT Bit 5
R/W
0x0
SIR Receiver Pulse Polarity Invert
0: Not invert receiver signal
1: Invert receiver signal
SIR_TX_INVERT Bit 4
R/W
0x0
SIR Transmit Pulse Polarity Invert
0: Not invert transmit pulse
1: Invert transmit pulse
Unused Bit 3
CHANGE_UPDATE Bit 2
R/WAC
0x0
After the user uses HALT[1] to change the baud rate or LCR configuration,
write 1 to update the configuration and wait this bit to self-clear to 0 to
finish update process. Writing 0 to this bit has no effect.
1: Update trigger, Self clear to 0 when finish update.
CHCFG_AT_BUSY Bit 1
R/W
0x0
This is an enable bit for the user to change LCR register configuration and
baud rate register (DLH and DLL) when the UART is busy.
1: Enable change when busy
HALT_TX Bit 0
R/W
0x0
Halt TX
This register is used to halt transmissions for testing, so that the transmit
FIFO can be filled by the master when FIFOs are implemented and enabled.
0 : Halt TX disabled
1 : Halt TX enabled
Note: If FIFOs are not enabled, the setting has no effect on operation.
Команда U-Boot для чтения регистра md 50000a4 1 md 50004a4 1 md 50008a4 1 md 5000ca4 1 md 50010a4 1 md 50014a4 1
Bit fields structure
typedef union uart_halt
{
struct
{
unsigned halt_tx : 1;
unsigned chcfg_at_busy : 1;
unsigned change_update : 1;
unsigned unused0 : 1;
unsigned sir_tx_invert : 1;
unsigned sir_rx_invert : 1;
unsigned dma_pte_rx : 1;
unsigned pte : 1;
unsigned unused1 : 24;
} b;
unsigned long w;
} UART_HALT
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