Регистры Allwinner H616

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UART_485_CTL
9.2.5. UART RS485 Control and Status Register - адрес: 0x50000c0 0x50004c0 0x50008c0 0x5000cc0 0x50010c0 0x50014c0 (смещение: 0x00C0)

Универсальный асинхронный приемо-передатчик: список регистров



31 ||||||||||||||||| 16
15 ||||||||||||||||| 00

  RESERV

Bits 31 : 7
R/W
0x0

Reserved


  AAD_ADDR_F

Bit 6
R/W1C
0x0

In AAD mode, when UART receives an address byte and the byte is the same
as RS485_ADDR_MATCH, this bit will be set to 1. If RS485 interrupt is
enabled, the RS485 interrupt will arrive.
Write 1 to clear this bit and reset the RS485 interrupt.


  RS485_ADDR_DET_F

Bit 5
R/W1C
0x0

This is a flag of the detected address bytes. When UART receives an address
byte, this bit will be set to 1. If the RS485 Interrupt is enabled, the RS485 interrupt will arrive.

1:An address byte is detected
0:No address byte is detected
Write 1 to clear this bit and reset the RS485 interrupt.


  Unused

Bit 4

  RX_BF_ADDR

Bit 3
R/W
0x0

In NMM mode, If setting this bit to 1, UART will receive all the bytes into
FIFO before receiving an address byte. If setting to 0, it will not.
1:Receive
0:Not Receive


  RX_AF_ADDR

Bit 2
R/W
0x0

In NMM mode, if setting this bit to 1, UART will receive all the bytes into
FIFO after receiving an address byte. If setting to 0, it will not.
1:Receive
0:Not Receive


  RS485_SLAVE_MODE_SEL

Bits 1 : 0
R/W
0x0

RS485 Slave Mode
00: Normal Multidrop Operation(NMM)
01: Auto Address Detection Operation(AAD)
10: Reserved
11: Reserved



Команда U-Boot для чтения регистра

md 50000c0 1
md 50004c0 1
md 50008c0 1
md 5000cc0 1
md 50010c0 1
md 50014c0 1



Bit fields structure

typedef union  uart_485_ctl
{
  struct
  {
   unsigned rs485_slave_mode_sel : 2;
   unsigned rx_af_addr : 1;
   unsigned rx_bf_addr : 1;
   unsigned unused0 : 1;
   unsigned rs485_addr_det_f : 1;
   unsigned aad_addr_f : 1;
   unsigned reserv : 25;
  } b;
   unsigned long w;
} UART_485_CTL
   

Allwinner H616 Manual