Регистры H616: SPI Global Control Register

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

SRST

Bit 31
R/WAC
0x0

Soft reset
Writing 1 to this bit will clear the SPI controller, and auto clear to '0' when
reset operation completes.
Writing '0' has no effect.

Unused

Bits 30 : 8

TP_EN

Bit 7
R/W
0x1

Transmit Pause Enable
In master mode, it is used to control transmit state machine to stop smart
burst sending when RX FIFO is full.
0: Normal operation, ignore RXFIFO status
1: Stop transmit data when RXFIFO full
Cannot be written when XCH=1

Unused

Bits 6 : 2

MODE

Bit 1
R/W
0x0

SPI Function Mode Select
0: Slave mode
1: Master mode
Cannot be written when XCH=1

ENA_CONTR

Bit 0
R/W
0x0

SPI Module Enable Control
0: Disable
1: Enable
After transforming from bit_mode to byte_mode, it must enable the SPI module again.

Bit fields structure

typedef union spi_gcr { struct { unsigned ena_contr : 1; unsigned mode : 1; unsigned unused0 : 5; unsigned tp_en : 1; unsigned unused1 : 23; unsigned srst : 1; } b; unsigned long w; } SPI_GCR