Синхронный последовательный интерфейс: список регистров

  XCH

Exchange Burst
In master mode it is used to start SPI burst
0: Idle
1: Initiates exchange.
Writing \"1\" to this bit will start the SPI burst, and will auto clear after finishing
the bursts transfer specified by BC. Writing \"1\" to SRST will also clear this bit.
Writing '0' to this bit has no effect.
Cannot be written when XCH=1.

  Unused

  SDDM

Sending Data Delay Mode
0:Normal sending
1:Delay sending
Set the bit to \"1\" to make the data that should be sent with a delay of half
cycle of SPI_CLK in dual IO mode for SPI mode 0.
Cannot be written when XCH=1.

  SDM

Master Sample Data Mode
0: Delay sample mode
1: Normal sample mode
In normal sample mode, SPI master samples the data at the correct edge for each SPI mode;
In delay sample mode, SPI master samples data at the edge that is half cycle delayed by the correct edge defined in respective SPI mode.
Cannot be written when XCH=1.

  FBS

First Transmit Bit Select
0: MSB first
1: LSB first
Cannot be written when XCH=1.

  SDC

Master Sample Data Control
Set this bit to 1 to make the internal read sample point with a delay of half
cycle of SPI_CLK. It is used in high speed read operation to reduce the error
caused by the time delay of SPI_CLK propagating between master and slave.
0: Normal operation, do not delay internal read sample point
1: Delay internal read sample point
Cannot be written when XCH=1.

  RPSM

Rapids Mode Select
Select rapid mode for high speed write.
0: Normal write mode
1: Rapid write mode
Cannot be written when XCH=1.

  DDB

Dummy Burst Type
0: The bit value of dummy SPI burst is zero
1: The bit value of dummy SPI burst is one
Cannot be written when XCH=1.

  DHB

Discard Hash Burst
In master mode it controls whether discarding unused SPI bursts
0: Receiving all SPI bursts in BC period
1: Discard unused SPI bursts, only fetching the SPI bursts during dummy burst period.
The bursts number is specified by TC.
Cannot be written when XCH=1.

  SS_LEVEL

When control SS signal manually (SPI_CTRL_REG.SS_CTRL==1), set this bit to
1 or '0' to control the level of SS signal.
0: set SS to low
1: set SS to high
Cannot be written when XCH=1.

  SS_OWNER

SS Output Owner Select
Usually, controller sends SS signal automatically with data together. When this
bit is set to 1, software must manually write SPI_CTL_REG.SS_LEVEL to 1 or 0
to control the level of SS signal.
0: SPI controller
1: Software
Cannot be written when XCH=1.

  SS_SEL

SPI Chip Select
Select one of four external SPI Master/Slave Devices
00: SPI_SS0 will be asserted
01: SPI_SS1 will be asserted
10: SPI_SS2 will be asserted
11: SPI_SS3 will be asserted
Cannot be written when XCH=1.

  SSCTL

In master mode, this bit selects the output wave form for the SPI_SSx signal.
Only valid when SS_OWNER = 0.
0: SPI_SSx remains asserted between SPI bursts
1: Negate SPI_SSx between SPI bursts
Cannot be written when XCH=1.

  SPOL

SPI Chip Select Signal Polarity Control
0: Active high polarity (0 = Idle)
1: Active low polarity (1 = Idle)
Cannot be written when XCH=1.

  CPOL

SPI Clock Polarity Control
0: Active high polarity (0 = Idle)
1: Active low polarity (1 = Idle)
Cannot be written when XCH=1.

  CPHA

SPI Clock/Data Phase Control
0: Phase 0 (Leading edge for sample data)
1: Phase 1 (Leading edge for setup data)
Cannot be written when XCH=1.

Команда U-Boot для чтения регистра

Bit fields structure

typedef union  spi_tcr
{
  struct
  {
   unsigned cpha : 1;
   unsigned cpol : 1;
   unsigned spol : 1;
   unsigned ssctl : 1;
   unsigned ss_sel : 2;
   unsigned ss_owner : 1;
   unsigned ss_level : 1;
   unsigned dhb : 1;
   unsigned ddb : 1;
   unsigned rpsm : 1;
   unsigned sdc : 1;
   unsigned fbs : 1;
   unsigned sdm : 1;
   unsigned sddm : 1;
   unsigned unused0 : 16;
   unsigned xch : 1;
  } b;
   unsigned long w;
} SPI_TCR