Unused Bits 31 : 14
SSI Bit 13
R/W1C
0x0
SS Invalid Interrupt
When SSI is 1, it indicates that SS has changed from valid state to invalid state.
Writing 1 to this bit clears it.
TRANSFER_COMPLETED Bit 12
R/W1C
0x0
In master mode, it indicates that all bursts specified by BC have been exchanged.
In other condition, When set, this bit indicates that all the datas in
TXFIFO have been loaded in the Shift register, and the Shift register has
shifted out all the bits. Writing 1 to this bit clears it.
0: Busy
1: Transfer completed
TF_UDF Bit 11
R/W1C
0x0
TXFIFO Underrun
This bit is set when if the TXFIFO is underrun. Writing 1 to this bit clears it.
0: TXFIFO is not underrun
1: TXFIFO is underrun
TF_OVF Bit 10
R/W1C
0x0
TXFIFO Overflow
This bit is set when if the TXFIFO is overflow. Writing 1 to this bit clears it.
0: TXFIFO is not overflow
1: TXFIFO is overflowed
RX_UDF Bit 9
R/W1C
0x0
RXFIFO Underrun
When set, this bit indicates that RXFIFO has underrun. Writing 1 to this bit
clears it.
RX_OVF Bit 8
R/W1C
0x0
RXFIFO Overflow
When set, this bit indicates that RXFIFO has overflowed. Writing 1 to this bit
clears it.
0: RXFIFO is available
1: RXFIFO is overflowed
Unused Bit 7
TX_FULL Bit 6
R/W1C
0x0
TXFIFO Full
This bit is set when if the TXFIFO is full . Writing 1 to this bit clears it.
0: TXFIFO is not Full
1: TXFIFO is Full
TX_EMP Bit 5
R/W1C
0x1
TXFIFO Empty
This bit is set if the TXFIFO is empty. Writing 1 to this bit clears it.
0: TXFIFO contains one or more words.
1: TXFIFO is empty
TX_READY Bit 4
R/W1C
0x1
TXFIFO Ready
0: TX_WL > TX_TRIG_LEVEL
1: TX_WL <= TX_TRIG_LEVEL
This bit is set any time if TX_WL <= TX_TRIG_LEVEL. Writing \"1\" to this bit
clears it. TX_WL is the water level of TXFIFO.
Unused Bit 3
RX_FULL Bit 2
R/W1C
0x0
RXFIFO Full
This bit is set when the RXFIFO is full . Writing 1 to this bit clears it.
0: Not Full
1: Full
RX_EMP Bit 1
R/W1C
0x1
RXFIFO Empty
This bit is set when the RXFIFO is empty . Writing 1 to this bit clears it.
0: Not empty
1: empty
RX_RDY Bit 0
R/W1C
0x0
RXFIFO Ready
0: RX_WL < RX_TRIG_LEVEL
1: RX_WL >= RX_TRIG_LEVEL
This bit is set any time if RX_WL >= RX_TRIG_LEVEL. Writing \"1\" to this bit
clears it. RX_WL is the water level of RXFIFO.
Команда U-Boot для чтения регистра md 5010014 1 md 5011014 1
Bit fields structure
typedef union spi_isr
{
struct
{
unsigned rx_rdy : 1;
unsigned rx_emp : 1;
unsigned rx_full : 1;
unsigned unused0 : 1;
unsigned tx_ready : 1;
unsigned tx_emp : 1;
unsigned tx_full : 1;
unsigned unused1 : 1;
unsigned rx_ovf : 1;
unsigned rx_udf : 1;
unsigned tf_ovf : 1;
unsigned tf_udf : 1;
unsigned transfer_completed : 1;
unsigned ssi : 1;
unsigned unused2 : 18;
} b;
unsigned long w;
} SPI_ISR
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