Синхронный последовательный интерфейс: список регистров

  Unused

  SSI

SS Invalid Interrupt
When SSI is 1, it indicates that SS has changed from valid state to invalid state.
Writing 1 to this bit clears it.

  TRANSFER_COMPLETED

In master mode, it indicates that all bursts specified by BC have been exchanged.
In other condition, When set, this bit indicates that all the datas in
TXFIFO have been loaded in the Shift register, and the Shift register has
shifted out all the bits. Writing 1 to this bit clears it.
0: Busy
1: Transfer completed

  TF_UDF

TXFIFO Underrun
This bit is set when if the TXFIFO is underrun. Writing 1 to this bit clears it.
0: TXFIFO is not underrun
1: TXFIFO is underrun

  TF_OVF

TXFIFO Overflow
This bit is set when if the TXFIFO is overflow. Writing 1 to this bit clears it.
0: TXFIFO is not overflow
1: TXFIFO is overflowed

  RX_UDF

RXFIFO Underrun
When set, this bit indicates that RXFIFO has underrun. Writing 1 to this bit
clears it.

  RX_OVF

RXFIFO Overflow
When set, this bit indicates that RXFIFO has overflowed. Writing 1 to this bit
clears it.
0: RXFIFO is available
1: RXFIFO is overflowed

  Unused

  TX_FULL

TXFIFO Full
This bit is set when if the TXFIFO is full . Writing 1 to this bit clears it.
0: TXFIFO is not Full
1: TXFIFO is Full

  TX_EMP

TXFIFO Empty
This bit is set if the TXFIFO is empty. Writing 1 to this bit clears it.
0: TXFIFO contains one or more words.
1: TXFIFO is empty

  TX_READY

TXFIFO Ready
0: TX_WL > TX_TRIG_LEVEL
1: TX_WL <= TX_TRIG_LEVEL
This bit is set any time if TX_WL <= TX_TRIG_LEVEL. Writing \"1\" to this bit
clears it. TX_WL is the water level of TXFIFO.

  Unused

  RX_FULL

RXFIFO Full
This bit is set when the RXFIFO is full . Writing 1 to this bit clears it.
0: Not Full
1: Full

  RX_EMP

RXFIFO Empty
This bit is set when the RXFIFO is empty . Writing 1 to this bit clears it.
0: Not empty
1: empty

  RX_RDY

RXFIFO Ready
0: RX_WL < RX_TRIG_LEVEL
1: RX_WL >= RX_TRIG_LEVEL
This bit is set any time if RX_WL >= RX_TRIG_LEVEL. Writing \"1\" to this bit
clears it. RX_WL is the water level of RXFIFO.

Команда U-Boot для чтения регистра

Bit fields structure

typedef union  spi_isr
{
  struct
  {
   unsigned rx_rdy : 1;
   unsigned rx_emp : 1;
   unsigned rx_full : 1;
   unsigned unused0 : 1;
   unsigned tx_ready : 1;
   unsigned tx_emp : 1;
   unsigned tx_full : 1;
   unsigned unused1 : 1;
   unsigned rx_ovf : 1;
   unsigned rx_udf : 1;
   unsigned tf_ovf : 1;
   unsigned tf_udf : 1;
   unsigned transfer_completed : 1;
   unsigned ssi : 1;
   unsigned unused2 : 18;
  } b;
   unsigned long w;
} SPI_ISR