Синхронный последовательный интерфейс: список регистров

  TX_FIFO_RST

TX FIFO Reset
Writing 1 to this bit will reset the control portion of the TX FIFO and auto
clear to '0' when completing reset operation, writing to '0' has no effect.

  TF_TEST_ENB

TX Test Mode Enable
0: Disable
1: Enable
Note: In normal mode, TX FIFO can only be read by SPI controller, writing 1
to this bit will switch TX FIFO read and write function to AHB bus. This bit is
used to test the TX FIFO, donot set in normal operation and donot set
RF_TEST and TF_TEST at the same time.

  Unused

  TF_DRQ_EN

TX FIFO DMA Request Enable
0: Disable
1: Enable

  TX_TRIG_LEVEL

TX FIFO Empty Request Trigger Level

  RF_RST

RXFIFO Reset
Writing 1 to this bit will reset the control portion of the receiver FIFO, and
auto clear to '0' when completing reset operation, writing '0' to this bit has no effect.

  RF_TEST

RX Test Mode Enable
0: Disable
1: Enable
Note: In normal mode, RX FIFO can only be written by SPI controller, writing
1 to this bit will switch RX FIFO read and write function to AHB bus.
This bit is used to test the RX FIFO, donot set in normal operation and donot set
RF_TEST and TF_TEST at the same time.

  Unused

  RF_DRQ_EN

RX FIFO DMA Request Enable
0: Disable
1: Enable

  RX_TRIG_LEVEL

RX FIFO Ready Request Trigger Level

Команда U-Boot для чтения регистра

Bit fields structure

typedef union  spi_fcr
{
  struct
  {
   unsigned rx_trig_level : 8;
   unsigned rf_drq_en : 1;
   unsigned unused0 : 5;
   unsigned rf_test : 1;
   unsigned rf_rst : 1;
   unsigned tx_trig_level : 8;
   unsigned tf_drq_en : 1;
   unsigned unused1 : 5;
   unsigned tf_test_enb : 1;
   unsigned tx_fifo_rst : 1;
  } b;
   unsigned long w;
} SPI_FCR