Синхронный последовательный интерфейс: список регистров

  Unused

  SWC

Dual mode direction switch wait clock counter (for master mode only).
Cannot be written when XCH=1.
0: No wait states inserted
n: n SPI_SCLK wait states inserted
Note: These bits control the number of wait states to be inserted before start
dual data transfer in dual SPI mode. The SPI module counts SPI_SCLK by SWC
for delaying next word data transfer.

  WCC

Wait Clock Counter (In master mode)
These bits control the number of wait states to be inserted in data transfers.
The SPI module counts SPI_SCLK by WCC for delaying next word data transfer.
0: No wait states inserted
N: N SPI_SCLK wait states inserted

Команда U-Boot для чтения регистра

Bit fields structure

typedef union  spi_wcr
{
  struct
  {
   unsigned wcc : 16;
   unsigned swc : 4;
   unsigned unused0 : 12;
  } b;
   unsigned long w;
} SPI_WCR