Регистры H616: SPI Clock Rate Control Register

SPI_CCR

9.3.5. SPI Clock Rate Control Register - адрес: 0x5010024 0x5011024 (смещение: 0x0024)

Синхронный последовательный интерфейс: список регистров

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

Unused

Bits 31 : 13

DRS

Bit 12
R/W
0x0

Divide Rate Select (Master Mode Only)
0: Select Clock Divide Rate 1
1: Select Clock Divide Rate 2
Cannot be written when XCH=1.

CDR1_M

Bits 11 : 8
R/W
0x0

Clock Divide Rate 1 (Master Mode Only)
The SPI_SCLK is determined according to the following equation: SPI_CLK =
Source_CLK / (2^CDR1_M).
Cannot be written when XCH=1.

CDR2_N

Bits 7 : 0
R/W
0x2

Clock Divide Rate 2 (Master Mode Only)
The SPI_SCLK is determined according to the following equation: SPI_CLK =
Source_CLK / (2*(CDR2_N + 1)).
Cannot be written when XCH=1.

Bit fields structure

typedef union spi_ccr { struct { unsigned cdr2_n : 8; unsigned cdr1_m : 4; unsigned drs : 1; unsigned unused0 : 19; } b; unsigned long w; } SPI_CCR