Регистры Allwinner H616

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SPI_BCC
9.3.5. SPI Burst Control Register - адрес: 0x5010038 0x5011038 (смещение: 0x0038)

Синхронный последовательный интерфейс: список регистров



31 ||||||||||||||||| 16
15 ||||||||||||||||| 00

  Unused

Bits 31 : 30

  QUAD_EN

Bit 29
R/W
0x0

Quad_Mode_EN
0: Quad mode disable
1: Quad mode enable
Cannot be written when XCH=1.
Note: Quad mode includes Quad-Input and Quad-Output.


  DRM

Bit 28
R/W
0x0

Master Dual Mode RX Enable
0: RX use single-bit mode
1: RX use dual mode
Cannot be written when XCH=1.
It is only valid when Quad_Mode_EN=0.


  DBC

Bits 27 : 24
R/W
0x0

Master Dummy Burst Counter
In master mode, this field specifies the burst number that should be sent
before receive in dual SPI mode. The data does not care by the device.
0: 0 burst
1: 1 burst
***
N: N bursts
Cannot be written when XCH=1.


  STC

Bits 23 : 0
R/W
0x0

Master Single Mode Transmit Counter
In master mode, this field specifies the burst number that should be sent in
single mode before automatically sending dummy burst. This is the first
transmit counter in all bursts.
0: 0 burst
1: 1 burst
***
N: N bursts
Cannot be written when XCH=1.



Команда U-Boot для чтения регистра

md 5010038 1
md 5011038 1



Bit fields structure

typedef union  spi_bcc
{
  struct
  {
   unsigned stc : 24;
   unsigned dbc : 4;
   unsigned drm : 1;
   unsigned quad_en : 1;
   unsigned unused0 : 2;
  } b;
   unsigned long w;
} SPI_BCC
   

Allwinner H616 Manual