Синхронный последовательный интерфейс: список регистров

  TCE

Transfer Control Enable
In master mode, it is used to start to transfer the serial bits frame, it is only
valid when Work Mode Select==0x10/0x11.
0: Idle
1: Initiates transfer
Writing \"1\" to this bit will start to transfer serial bits frame(the value comes
from the SPI TX Bit Register or SPI RX Bit Register), and will auto clear after
the bursts transfer completely. Writing '0' to this bit has no effect.

  MSMS

Master Sample Standard
0: Delay Sample Mode
1: Standard Sample Mode
In Standard Sample Mode, SPI master samples the data at the standard
rising edge of SCLK for each SPI mode;
In Delay Sample Mode, SPI master samples data at the edge that is half cycle
delayed by the standard rising edge of SCLK defined in respective SPI mode.

  Unused

  TBC

Transfer Bits Completed
When set, this bit indicates that the last bit of the serial data frame in SPI TX
Bit Register(or SPI RX Bit Register) has been transferred completely. Writing 1
to this bit clears it.
0: Busy
1: Transfer Completed
It is only valid when Work Mode Select==0x10/0x11.

  TBC_INT_EN

Transfer Bits Completed Interrupt Enable
0: Disable
1: Enable
It is only valid when Work Mode Select==0x10/0x11.

  Unused

  LEN_FRAME_RX

Configure the length of serial data frame(burst) of RX
000000: 0bit
000001: 1bit
***
100000: 32bits
Other values: reserved
It is only valid when Work Mode Select==0x10/0x11, and cannot be written when TCE=1.

  Unused

  LEN_FRAME_TX

Configure the length of serial data frame(burst) of TX
000000: 0bit
000001: 1bit
***
100000: 32bits
Other values: reserved
It is only valid when Work Mode Select==0x10/0x11, and cannot be written when TCE=1.

  SS_LEVEL

When control SS signal manually , set this bit to 1 or '0' to control the level of
SS signal.
0: Set SS to low
1: Set SS to high
It is only valid when Work Mode Select==0x10/0x11, and only work in Mode0, cannot be written when TCE=1.

  SS_OWNER

SS Output Owner Select
Usually, controller sends SS signal automatically with data together. When this
bit is set to 1, software must manually write SPI_CTL_REG.SS_LEVEL to 1 or 0
to control the level of SS signal.
0: SPI controller
1: Software
It is only valid when Work Mode Select==0x10/0x11, and only work in Mode0, cannot be written when TCE=1.

  SPOL

SPI Chip Select Signal Polarity Control
0: Active high polarity (0 = Idle)
1: Active low polarity (1 = Idle)
It is only valid when Work Mode Select==0x10/0x11, and only work in Mode0, cannot be written when TCE=1.

  Unused

  SS_SEL

SPI Chip Select
Select one of four external SPI Master/Slave Devices
00: SPI_SS0 will be asserted
01: SPI_SS1 will be asserted
10: SPI_SS2 will be asserted
11: SPI_SS3 will be asserted
It is only valid when Work Mode Select= =0x10/0x11, and only work in
Mode0, cannot be written when TCE=1.

  WM_SEL

Work Mode Select
00: Data frame is byte aligned in standard SPI, dual-output/dual input SPI, dual IO SPI and quad-output/quad-input SPI.
01: Reserved
10: Data frame is bit aligned in 3-wire SPI
11: Data frame is bit aligned in standard SPI

Команда U-Boot для чтения регистра

Bit fields structure

typedef union  spi_batcr
{
  struct
  {
   unsigned wm_sel : 2;
   unsigned ss_sel : 2;
   unsigned unused0 : 1;
   unsigned spol : 1;
   unsigned ss_owner : 1;
   unsigned ss_level : 1;
   unsigned len_frame_tx : 6;
   unsigned unused1 : 2;
   unsigned len_frame_rx : 6;
   unsigned unused2 : 2;
   unsigned tbc_int_en : 1;
   unsigned tbc : 1;
   unsigned unused3 : 4;
   unsigned msms : 1;
   unsigned tce : 1;
  } b;
   unsigned long w;
} SPI_BATCR