Хост-контроллер USB2.0: список регистров

  Unused

  INTERRUPT_THRESHOLD_CONTROL

The value in this field is used by system software to select the maximum
rate at which the host controller will issue interrupts.
The only valid values are defined below:
Value: Minimum Interrupt Interval
0x00: Reserved
0x01: 1 micro-frame
0x02: 2 micro-frame
0x04: 4 micro-frame
0x08: 8 micro-frame(default, equates to 1 ms)
0x10: 16 micro-frame(2ms)
0x20: 32 micro-frame(4ms)
0x40: 64 micro-frame(8ms)
Any other value in this register yields undefined results.
The default value in this field is 0x08 .
Software modifications to this bit while HC Halted bit is equal to zero results in undefined behavior.

  Unused

  ASYN_SCHED_PM_ENA

Asynchronous Schedule Park Mode Enable(OPTIONAL)
If the Asynchronous Park Capability bit in the HCCPARAMS register is a one,
then this bit defaults to a 1 and is R/W. Otherwise the bit must be a zero and
is Read Only. Software uses this bit to enable or disable Park mode.
When this bit is one, Park mode is enabled. When this bit is zero, Park mode is disabled.

  Unused

  ASYN_SCHED_PM_COUNT

Asynchronous Schedule Park Mode Count(OPTIONAL)
Asynchronous Park Capability bit in the HCCPARAMS register is a one,
Then this field defaults to 0x3 and is W/R. Otherwise it defaults to zero and is R.
It contains a count of the number of successive transactions the host
controller is allowed to execute from a high-speed queue head on the
Asynchronous schedule before continuing traversal of the Asynchronous schedule.
Valid value are 0x1 to 0x3.Software must not write a zero to this bit when
Park Mode Enable is a one as it will result in undefined behavior.

  LIGHT_HOST_CONTR_RES

Light Host Controller Reset(OPTIONAL)
This control bit is not required.
If implemented, it allows the driver to reset the EHCI controller without
affecting the state of the ports or relationship to the companion host controllers.
For example, the PORSTC registers should not be reset to their
default values and the CF bit setting should not go to zero (retaining port
ownership relationships).
A host software read of this bit as zero indicates the Light Host Controller
Reset has completed and it si safe for software to re-initialize the host
controller. A host software read of this bit as a one indicates the Light Host

  INTER_ASYNC_ADV_DOORBELL

Interrupt on Async Advance Doorbell
This bit is used as a doorbell by software to tell the host controller to issue
an interrupt the next time it advances asynchronous schedule. Soft-
Ware must write a 1 to this bit to ring the doorbell.
When the host controller has evicted all appropriate cached schedule state,
it sets the Interrupt on Async Advance status bit in the USBSTS. if the
Interrupt on Async Advance Enable bit in the USBINTR register is a one then
the host controller will assert an interrupt at the next interrupt threshold.
The host controller sets this bit to a zero after it has set the Interrupt on
Async Advance status bit in the USBSTS register to a one.
Software should not write a one to this bit when the asynchronous schedule
is disabled. Doing so will yield undefined results.

  ASYNCH_SCHED_ENA

Asynchronous Schedule Enable
This bit
controls whether the host controller skips processing the Asynchronous Schedule.

Bit Value: Meaning
0: Do not process the Asynchronous Schedule.
1: Use the ASYNLISTADDR register to access the Asynchronous Schedule.
The default value of this field is '0b'.

  APERIOD_SCHED_ENA

Periodic Schedule Enable
This bit controls whether the host controller skips processing the Periodic Schedule.

Bit Value: Meaning
0: Do not process the Periodic Schedule. Use the PERIODICLISTBASE register to access the
1: Periodic Schedule.
The default value of this field is '0b'.

  FRAME_LIST_SIZE

Frame List Size
This field is R/W only if Programmable Frame List Flag in the HCCPARAMS
registers is set to a one. This field specifies the size of the Frame list.
The size the frame list controls which bits in the Frame Index Register should be used for the Frame List Current index.

Bits: Meaning
00: 1024 elements(4096 bytes)Default value
01: 512 elements(2048 byts)
10: 256 elements (1024 bytes) For resource-constrained condition
11: reserved
The default value is '00b'.

  HOST_CONTROLLER_RESET

Host Controller Reset
This control bit is used by software to reset the host controller.
The effects of this on Root Hub registers are similar to a Chip Hardware Reset.
When software writes a one to this bit, the Host Controller resets its internal
pipelines, timers, counters, state machines, etc. to their initial value.
Any transaction currently in progress on USB is immediately terminated.
A USB reset is not driven on downstream ports.
All operational registers, including port registers and port state machines
are set to their initial values. Port ownership reverts to the companion host
controller(s). Software must reinitialize the host controller as described in
Section 4.1 of the CHEI Specification in order to return the host controller to
an operational state.
This bit is set to zero by the Host Controller when the reset process is
complete. Software cannot terminate the reset process early by writing a
zero to this register.
Software should not set this bit to a one when the HC Halted bit in the
USBSTS register is a zero. Attempting to reset an actively running host
controller will result in undefined behavior.

  RUN_STOP

Run/Stop
When set to a 1, the Host Controller proceeds with execution of the schedule.
When set to 0, the Host Controller completes the current and any actively pipelined transactions on the USB and then halts.
The Host Controller must halt within 16 micro-frames after software clears this bit.
The HC Halted bit indicates when the Host Controller has finished its pending pipelined transactions and has entered the stopped state.
Software must not write a one to this field unless the Host Controller is in the Halt State.
The default value is 0x0.

Команда U-Boot для чтения регистра

Bit fields structure

typedef union  e_usbcmd
{
  struct
  {
   unsigned run_stop : 1;
   unsigned host_controller_reset : 1;
   unsigned frame_list_size : 2;
   unsigned aperiod_sched_ena : 1;
   unsigned asynch_sched_ena : 1;
   unsigned inter_async_adv_doorbell : 1;
   unsigned light_host_contr_res : 1;
   unsigned asyn_sched_pm_count : 2;
   unsigned unused0 : 1;
   unsigned asyn_sched_pm_ena : 1;
   unsigned unused1 : 4;
   unsigned interrupt_threshold_control : 8;
   unsigned unused2 : 8;
  } b;
   unsigned long w;
} E_USBCMD