Хост-контроллер USB2.0: список регистров

  Unused

  ASYNCHR_SCHED_STAT

Asynchronous Schedule Status
The bit reports the current real status of Asynchronous Schedule. If this bit is
a zero then the status of the Asynchronous Schedule is disabled. If this bit is
a one then the status of the Asynchronous Schedule is enabled.
The Host Controller is not required to immediately disable or enable the
Asynchronous Schedule when software transitions the Asynchronous
Schedule Enable bit in the USBCMD register.
When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous
Schedule is either enabled (1) or disabled (0).

  PERIOD_SCHED_STAT

Periodic Schedule Status

The bit reports the current real status of the Periodic Schedule. If this bit is a
zero then the status of the Periodic Schedule is disabled.
If this bit is a one then the status of the Periodic Schedule is enabled.
The Host Controller is not required to immediately disable or enable the Periodic Schedule when
software transitions the Periodic Schedule Enable bit in the USBCMD register.
When this bit and the Periodic Schedule Enable bit are the same
value, the Periodic Schedule is either enabled (1) or disabled (0).

  RECLAMATION

This is a read-only status bit, which is used to detect an empty asynchronous schedule.

  HC_HALTED

This bit is a zero whenever the Run/Stop bit is a one. The Host Controller
Sets this bit to one after it has stopped executing as a result of the Run/Stop
bit being set to 0, either by software or by the Host Controller Hardware (e.g. internal error).
The default value is 1 .

  Unused

  INTER_ASYNC_ADVANCE

Interrupt on Async Advance
System software can force the host controller to issue an interrupt the next
time the host controller advances the asynchronous schedule by writing a
one to the Interrupt on Async Advance Doorbell bit in the USBCMD register.
This status bit indicates the assertion of that interrupt source.

  HOST_SYSTEM_ERROR

The Host Controller set this bit to 1 when a serious error occurs during a host system access involving the Host Controller module.
When this error occurs, the Host Controller clears the Run/Stop bit in the Command register to prevent further execution of the scheduled TDs.

  FRAME_LIST_ROLLOVER

The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero.
The exact value at which the rollover occurs depends on the frame list size.
For example, if the frame list size is 1024, the Frame Index Register rolls over every time FRINDEX [13] toggles.
Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX [12] toggles.

  PORT_CHANGE_DETECT

The Host Controller sets this bit to a one when any port for which the Port
Owner bit is set to zero has a change bit transition from a zero to a one or a
Force Port Resume bit transition from a zero to a one as a result of a J-K
transition detected on a suspended port.
This bit will also be set as a result of the Connect Status Chang being set to a one after system software has
relinquished ownership of a connected port by writing a one to a port's Port Owner bit.

  USB_ERR_INT

USB Error Interrupt
The Host Controller sets this bit to 1 when completion of USB transaction results in an error condition (e.g. error counter underflow).
If the TD on which the error interrupt occurred also had its IOC bit set, both.
This bit and USBINT bit are set.

  USB_INT

USB Interrupt
The Host Controller sets this bit to a one on the completion of a USB
transaction, which results in the retirement of a Transfer Descriptor that had its IOC bit set.

The Host Controller also sets this bit to 1 when a short packet is detected
(actual number of bytes received was less than the expected number of bytes)

Команда U-Boot для чтения регистра

Bit fields structure

typedef union  e_usbsts
{
  struct
  {
   unsigned usb_int : 1;
   unsigned usb_err_int : 1;
   unsigned port_change_detect : 1;
   unsigned frame_list_rollover : 1;
   unsigned host_system_error : 1;
   unsigned inter_async_advance : 1;
   unsigned unused0 : 6;
   unsigned hc_halted : 1;
   unsigned reclamation : 1;
   unsigned period_sched_stat : 1;
   unsigned asynchr_sched_stat : 1;
   unsigned unused1 : 16;
  } b;
   unsigned long w;
} E_USBSTS