31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00
Unused
Bits
31 :
11
REMOTE_WAKEUP_ENABLE
Bit
10R/W (R)
0x0
This bit is used by HCD to enable or disable the remote wakeup feature upon the detection of upstream resume signaling.
When this bit is set and the ResumeDetected bit in HcInterruptStatus is set, a remote wakeup is signaled to the host system.
Setting this bit has no impact on the generation of hardware interrupt.
REMOTE_WAKEUP_CONNECTED
Bit
9R/W (R/W
0x0
This bit indicates whether HC supports remote wakeup signaling.
If remote wakeup is supported and used by the system, it is the responsibility of system firmware to set this bit during POST.
HC clear the bit upon a hardware reset but does not alter it upon a software reset.
Remote wakeup signaling of the host system is host-bus-specific and is not described in this specification.
INTERRUPT_ROUTING
Bit
8R/W (R)
0x0
This bit determines the routing of interrupts generated by events registered in HcInterruptStatus.
If clear, all interrupt are routed to the normal host bus interrupt mechanism.
If set interrupts are routed to the System
Management Interrupt.
HCD clears this bit upon a hardware reset, but it
does not alter this bit upon a software reset. HCD uses this bit as a tag to
indicate the ownership of HC.
HOST_CONTR_FUNC_STATE
Bits
7 :
6R/W (R/W
0x0
Host Controller Functional State for USB
00: USB Reset
01: USB Resume
10: USBO perational
11: USB_Suspend
A transition to USBOperational from another state causes SOF generation to begin 1 ms later.
HCD may determine whether HC has begun sending SOFs by reading the START_OF_FRAME field of Hc Interrupt Status.
This field may be changed by HC only when in the USBSUSPEND state.
HC may move from the USBSUSPEND state to the USBRESUME state after detecting the resume signaling from a downstream port.
HC enters USBSUSPEND after a software reset, whereas it enters USBRESET after a hardware reset.
The latter also resets the Root Hub and asserts subsequent reset signaling to downstream ports.
BULK_LIST_ENABLE
Bit
5R/W (R)
0x0
This bit is set to enable the processing of the Bulk list in the next Frame.
If cleared by HCD, processing of the Bulk list does not occur after the next SOF.
HC checks this bit whenever it determines to process the list.
When disabled, HCD may modify the list.
If HcBulkCurrentED is pointing to an ED to be removed, HCD must advance the pointer by updating HcBulkCurrentED before re-enabling processing of the list.
CONTROL_LIST_ENABLE
Bit
4R/W (R)
0x0
This bit is set to enable the processing of the Control list in the next Frame.
If cleared by HCD, processing of the Control list does not occur after the next SOF.
HC must check this bit whenever it determines to process the list.
When disabled, HCD may modify the list.
If HcControlCurrentED is pointing to an ED to be removed, HCD must advance the pointer by updating HcControlCurrentED before re-enabling processing of the list.
ISOCHRONOUS_ENABLE
Bit
3R/W (R)
0x0
This bit is used by HCD to enable/disable processing of isochronous EDs.
While processing the periodic list in a Frame, HC checks the status of this bit when it finds an Isochronous ED (F=1).
If set (enabled), HC continues processing the EDs.
If cleared (disabled), HC halts processing of the periodic list
(which now contains only isochronous EDs) and begins processing the Bulk/Control lists.
Setting this bit is guaranteed to take effect in the next Frame (not the current Frame).
PERIODIC_LIST_ENABLE
Bit
2R/W (R)
0x0
This bit is set to enable the processing of periodic list in the next Frame.
If cleared by HCD, processing of the periodic list does not occur after the next SOF.
HC must check this bit before it starts processing the list.
CONTROL_BULK_SERVICE_RATIO
Bits
1 :
0R/W (R)
0x0
This specifies the service ratio between Control and Bulk EDs.
Before processing any of the nonperiodic lists, HC must compare the ratio specified
with its internal count on how many nonempty Control EDs have been processed,
in determining whether to continue serving another Control ED or switching to Bulk EDs.
The internal count will be retained when crossing the frame boundary.
In case of reset, HCD is responsible for restoring this value.
CBSR: No. of Control EDs Over Bulk EDs Served
0: 1-1
1: 2-1
2: 3-1
3: 4-1
The default value is 0x0.
Note: For field Read/Write :
1) HCD
2) HC