Регистры H616: LRADC Control Register

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

FIRST_CONVERT_DLY

Bits 31 : 24
R/W
0x1

ADC First Convert Delay Setting
ADC conversion is delayed by n samples.

Unused

Bits 23 : 20

CONTINUE_TIME_SELECT

Bits 19 : 16
R/W
0x0

Continue Mode Time Select
One of 8*(N+1) sample as a valuable sample data.

Unused

Bits 15 : 14

KEY_MODE_SELECT

Bits 13 : 12
R/W
0x0

Key Mode Select
00: Normal Mode
01: Single Mode
10: Continue Mode

LEVELA_B_CNT

Bits 11 : 8
R/W
0x1

Level A to Level B time threshold select, judge ADC convert value in level A to level B in n+1 samples.

LRADC_HOLD_KEY_EN

Bit 7
R/W
0x0

LRADC Hold KEY Enable
0: Disable
1: Enable

LRADC_CHANNEL_EN

Bit 6
R/W
0x1

LRADC Channel Enable
0: Disable
1: Enable

LEVELB_VOL.

Bits 5 : 4
R/W
0x2

Level B Corresponding Data Value Setting (the real voltage value)
00: 0x3C (1.266 V)
01: 0x39 (1.202 V)
10: 0x36 (1.139 V)
11: 0x33 (1.076 V)

LRADC_SAMPLE_RATE

Bits 3 : 2
R/W
0x2

LRADC Sample Rate
00: 2 kHz
01: 1 kHz
10: 500 Hz
11: 250 Hz

Unused

Bit 1

LRADC_EN

Bit 0
R/W
0x0

LRADC Enable
0: Disable
1: Enable

Bit fields structure

typedef union lradc_ctrl { struct { unsigned lradc_en : 1; unsigned unused0 : 1; unsigned lradc_sample_rate : 2; unsigned levelb_vol. : 2; unsigned lradc_channel_en : 1; unsigned lradc_hold_key_en : 1; unsigned levela_b_cnt : 4; unsigned key_mode_select : 2; unsigned unused1 : 2; unsigned continue_time_select : 4; unsigned unused2 : 4; unsigned first_convert_dly : 8; } b; unsigned long w; } LRADC_CTRL