Регистры H616: CIR Receiver Interrupt Control Register

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

Unused

Bits 31 : 14

RAL

Bits 13 : 8
R/W
0x0

RX FIFO available received byte level for interrupt and DMA request TRIGGER_LEVEL = RAL + 1

Unused

Bits 7 : 6

DRQ_EN

Bit 5
R/W
0x0

RX FIFO DMA Enable
0: Disable
1: Enable
When set to 1 , the Receiver FIFO DRQ is asserted if reaching RAL.
The DRQ is de-asserted when condition fails.

RAI_EN

Bit 4
R/W
0x0

RX FIFO Available Interrupt Enable
0: Disable
1: Enable
When set to 1 , the Receiver FIFO IRQ is asserted if reaching RAL.
The IRQ is de-asserted when condition fails.

Unused

Bits 3 : 2

RPEI_EN

Bit 1
R/W
0x0

Receiver Packet End Interrupt Enable
0: Disable
1: Enable

ROI_EN

Bit 0
R/W
0x0

Receiver FIFO Overrun Interrupt Enable
0: Disable
1: Enable

Bit fields structure

typedef union cir_rxint { struct { unsigned roi_en : 1; unsigned rpei_en : 1; unsigned unused0 : 2; unsigned rai_en : 1; unsigned drq_en : 1; unsigned unused1 : 2; unsigned ral : 6; unsigned unused2 : 18; } b; unsigned long w; } CIR_RXINT