Контроллер ШИМ: список регистров

  Unused

  PIS4

PWM Channel 4 Interrupt Status

When PWM channel 4 counter reaches Entire Cycle Value, this bit is set 1 by hardware.
Writing 1 to clear this bit.
Reads 0: PWM channel 4 interrupt is not pending.
Reads 1: PWM channel 4 interrupt is pending.
Writes 0: No effect.
Writes 1: Clear PWM channel 4 interrupt status.

  PIS3

PWM Channel 3 Interrupt Status
When PWM channel 3 counter reaches Entire Cycle Value, this bit is set 1 by hardware.
Writing 1 to clear this bit.
Reads 0: PWM channel 3 interrupt is not pending.
Reads 1: PWM channel 3 interrupt is pending.
Writes 0: No effect.
Writes 1: Clear PWM channel 3 interrupt status.

  PIS2

PWM Channel 2 Interrupt Status
When PWM channel 2 counter reaches Entire Cycle Value, this bit is set 1 by ardware.
Writing 1 to clear this bit.
Reads 0: PWM channel 2 interrupt is not pending.
Reads 1: PWM channel 2 interrupt is pending.
Writes 0: No effect.
Writes 1: Clear PWM channel 2 interrupt status.

  PIS1

PWM Channel 1 Interrupt Status
When PWM channel 1 counter reaches Entire Cycle Value, this bit is set 1 by hardware.
Writing 1 to clear this bit.
Reads 0: PWM channel 1 interrupt is not pending.
Reads 1: PWM channel 1 interrupt is pending.
Writes 0: No effect.
Writes 1: Clear PWM channel 1 interrupt status.

  Unused

Команда U-Boot для чтения регистра

Bit fields structure

typedef union  pisr
{
  struct
  {
   unsigned unused0 : 1;
   unsigned pis1 : 1;
   unsigned pis2 : 1;
   unsigned pis3 : 1;
   unsigned pis4 : 1;
   unsigned unused1 : 27;
  } b;
   unsigned long w;
} PISR