Unused Bits 31 : 10
CFIS4 Bit 9
R/W1C
0x0
Capturing channel 4 falling lock interrupt status.
When capturing channel 4 captures falling edge, if capturing channel 4 fall lock interrupt (CFIE4) is enabled, this bit is set 1 by hardware.
Writing 1 to clear this bit.
Reads 0: Capturing channel 4 interrupt is not pending.
Reads 1: Capturing channel 4 interrupt is pending.
Writes 0: No effect.
Writes 1: Clear capturing channel 4 interrupt status.
CRIS4 Bit 8
R/W1C
0x0
Capturing channel 4 rising lock interrupt status.
When capturing channel 4 captures rising edge, if capturing channel 4 rise lock interrupt (CRIE4) is enabled, this bit is set 1 by hardware.
Writing 1 to clear this bit.
Reads 0: Capturing channel 4 interrupt is not pending.
Reads 1: Capturing channel 4 interrupt is pending.
Writes 0: No effect.
Writes 1: Clear capturing channel 4 interrupt status.
CFIS3 Bit 7
R/W1C
0x0
Capture channel 3 falling lock interrupt status.
When capture channel 3 captures falling edge, if capture channel 3 fall lock interrupt (CFIE3) is enabled, this bit is set 1 by hardware.
Writing 1 to clear this bit.
Reads 0: Capture channel 3 interrupt is not pending.
Reads 1: Capture channel 3 interrupt is pending.
Writes 0: no effect.
Writes 1: Clear capture channel 3 interrupt status.
CRIS3 Bit 6
R/W1C
0x0
Capture channel 3 rising lock interrupt status.
When capture channel 3 captures rising edge, if capture channel 3 rise lock interrupt (CRIE3) is enabled, this bit is set 1 by hardware.
Writing 1 to clear this bit.
Reads 0: Capture channel 3 interrupt is not pending.
Reads 1: Capture channel 3 interrupt is pending.
Writes 0: no effect.
Writes 1: Clear capture channel 3 interrupt status.
CFIS2 Bit 5
R/W1C
0x0
Capture channel 2 falling lock interrupt status.
When capture channel 2 captures falling edge, if capture channel 2 fall lock interrupt (CFIE2) is enabled, this bit is set 1 by hardware.
Writing 1 to clear this bit.
Reads 0: Capture channel 2 interrupt is not pending.
Reads 1: Capture channel 2 interrupt is pending.
Writes 0: no effect.
Writes 1: Clear capture channel 2 interrupt status.
CRIS2 Bit 4
R/W1C
0x0
Capture channel 2 rising lock interrupt status.
When capture channel 2 captures rising edge, if capture channel 2 rise lock interrupt (CRIE2) is enabled, this bit is set 1 by hardware.
Writing 1 to clear this bit.
Reads 0: Capture channel 2 interrupt is not pending.
Reads 1: Capture channel 2 interrupt is pending.
Writes 0: no effect.
Writes 1: Clear capture channel 2 interrupt status.
CFIS1 Bit 3
R/W1C
0x0
Capture channel 1 falling lock interrupt status.
When capture channel 1 captures falling edge, if capture channel 1 fall lock interrupt (CFIE1) is enabled, this bit is set 1 by hardware.
Writing 1 to clear this bit.
Reads 0: Capture channel 1 interrupt is not pending.
Reads 1: Capture channel 1 interrupt is pending.
Writes 0: no effect.
Writes 1: Clear capture channel 1 interrupt status.
CRIS1 Bit 2
R/W1C
0x0
Capture channel 1 rising lock interrupt status.
When capture channel 1 captures rising edge, if capture channel 1 rise lock interrupt (CRIE1) is enabled, this bit is set 1 by hardware.
Writing 1 to clear this bit.
Reads 0: Capture channel 1 interrupt is not pending.
Reads 1: Capture channel 1 interrupt is pending.
Writes 0: no effect.
Writes 1: Clear capture channel 1 interrupt status.
Unused Bits 1 : 0
Команда U-Boot для чтения регистра md 300a014 1
Bit fields structure
typedef union cisr
{
struct
{
unsigned unused0 : 2;
unsigned cris1 : 1;
unsigned cfis1 : 1;
unsigned cris2 : 1;
unsigned cfis2 : 1;
unsigned cris3 : 1;
unsigned cfis3 : 1;
unsigned cris4 : 1;
unsigned cfis4 : 1;
unsigned unused1 : 22;
} b;
unsigned long w;
} CISR
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