IOMMU_L1PG_INT_REG Модуль управления памятью ввода-вывода IOMMU: список регистров 31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16 15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00 DBG_MODE_L1PG_INT Bit 31R 0x0 Debug mode address switch causes L1 page table to occur interrupt. Unused Bits 30 : 7MASTER6_L1PG_INT Bit 6R 0x0 Master6 address switch causes L1 page table to occur interrupt. MASTER5_L1PG_INT Bit 5R 0x0 Master5 address switch causes L1 page table to occur interrupt. MASTER4_L1PG_INT Bit 4R 0x0 Master4 address switch causes L1 page table to occur interrupt. MASTER3_L1PG_INT Bit 3R 0x0 Master3 address switch causes L1 page table to occur interrupt. MASTER2_L1PG_INT Bit 2R 0x0 Master2 address switch causes L1 page table to occur interrupt. MASTER1_L1PG_INT Bit 1R 0x0 Master1 address switch causes L1 page table to occur interrupt. MASTER0_L1PG_INT Bit 0R 0x0 Master0 address switch causes L1 page table to occur interrupt. Команда U-Boot для чтения регистра md 30f0180 1Bit fields structure
typedef union iommu_l1pg_int_reg
{
struct
{
unsigned master0_l1pg_int : 1;
unsigned master1_l1pg_int : 1;
unsigned master2_l1pg_int : 1;
unsigned master3_l1pg_int : 1;
unsigned master4_l1pg_int : 1;
unsigned master5_l1pg_int : 1;
unsigned master6_l1pg_int : 1;
unsigned unused0 : 24;
unsigned dbg_mode_l1pg_int : 1;
} b;
unsigned long w;
} IOMMU_L1PG_INT_REG
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