Unused Bits 31 : 26
TSG_STS Bits 25 : 24
R
0x0
Status for TS Generator
00: IDLE state
01: Running state
10: PAUSE state
Others: Reserved
Unused Bits 23 : 10
TSGL_BUF_MODE Bit 9
R/W
0x0
Loop Buffer Mode
When set to 1 , the TSG external buffer is in loop mode.
TSG_SYNC_BYTE_CHK_EN Bit 8
R/W
0x0
Sync Byte Check Enable
Enable/Disable check SYNC byte for receiving new packet
0: Disable
1: Enable
If enable check SYNC byte and an error SYNC byte is receiver.
TS Generator would come into PAUSE state.
If the correspond interrupt is enabled, the interrupt would happen.
Unused Bits 7 : 3
TSG_PAUSE_BIT Bit 2
R/W
0x0
Pause Bit for TS Generator
Write 1 to pause TS Generator.
TS Generator would stop fetch new data from DRAM.
After finished this operation, this bit will clear to zero by hardware.
In PAUSE state, write 1 to resume this state.
TSG_STOP_BIT Bit 1
R/W
0x0
Stop Bit for TS Generator
Write 1 to stop TS Generator.
TS Generator would stop fetch new data from DRAM.
The data already in its FIFO should be sent to TS filter.
After finished this operation, this bit will clear to zero by hardware.
TSG_START_BIT Bit 0
R/W
0x0
Start Bit for TS Generator
Write 1 to start TS Generator.
TS Generator would fetch data from DRAM and generate SPI stream to TS filter.
This bit will clear to zero by hardware after TS Generator is running.
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Bit fields structure
typedef union tsg_csr
{
struct
{
unsigned tsg_start_bit : 1;
unsigned tsg_stop_bit : 1;
unsigned tsg_pause_bit : 1;
unsigned unused0 : 5;
unsigned tsg_sync_byte_chk_en : 1;
unsigned tsgl_buf_mode : 1;
unsigned unused1 : 14;
unsigned tsg_sts : 2;
unsigned unused2 : 6;
} b;
unsigned long w;
} TSG_CSR
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