Регистры H616: TSG Interrupt Enable and Status Register

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

Unused

Bits 31 : 20

TSG_END_IE

Bit 19
R/W
0x0

TS Generator (TSG) End Interrupt Enable
0: Disable
1: Enable
If set this bit, the interrupt would assert to CPU when all data in external DRAM are sent to TS PID filter.

TSGFFIE

Bit 18
R/W
0x0

TS Generator (TSG) Full Finish Interrupt Enable
0: Disable
1: Enable

TSGHFIE

Bit 17
R/W
0x0

TS Generator (TSG) Half Finish Interrupt Enable
0: Disable
1: Enable

TSG_ERRSYNCBYTEIE

Bit 16
R/W
0x0

TS Generator (TSG) Error Sync Byte Interrupt Enable
0: Disable
1: Enable

Unused

Bits 15 : 4

TSG_END_STS

Bit 3
R/W1C
0x0

TS Generator (TSG) End Status
Write 1 to clear.

TSG_FF_STS

Bit 2
R/W1C
0x0

TS Generator (TSG) Full Finish Status
Write 1 to clear.

TSG_HF_STS

Bit 1
R/W1C
0x0

TS Generator (TSG) Half Finish Status
Write 1 to clear.

TSG_ERR_SYNC_BYTE_STS

Bit 0
R/W1C
0x0

TS Generator (TSG) Error Sync Byte Status
Write 1 to clear.

Bit fields structure

typedef union tsg_iesr { struct { unsigned tsg_err_sync_byte_sts : 1; unsigned tsg_hf_sts : 1; unsigned tsg_ff_sts : 1; unsigned tsg_end_sts : 1; unsigned unused0 : 12; unsigned tsg_errsyncbyteie : 1; unsigned tsghfie : 1; unsigned tsgffie : 1; unsigned tsg_end_ie : 1; unsigned unused1 : 12; } b; unsigned long w; } TSG_IESR