Регистры H616: PC External Interrupt Control Register

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

Unused

Bits 31 : 17

EINT16_CTL

Bit 16
R/W
0x0

External INT16 Enable
0: Disable
1: Enable

EINT15_CTL

Bit 15
R/W
0x0

External INT15 Enable
0: Disable
1: Enable

EINT14_CTL

Bit 14
R/W
0x0

External INT14 Enable
0: Disable
1: Enable

EINT13_CTL

Bit 13
R/W
0x0

External INT13 Enable
0: Disable
1: Enable

EINT12_CTL

Bit 12
R/W
0x0

External INT12 Enable
0: Disable
1: Enable

EINT11_CTL

Bit 11
R/W
0x0

External INT11 Enable
0: Disable
1: Enable

EINT10_CTL

Bit 10
R/W
0x0

External INT10 Enable
0: Disable
1: Enable

EINT9_CTL

Bit 9
R/W
0x0

External INT9 Enable
0: Disable
1: Enable

EINT8_CTL

Bit 8
R/W
0x0

External INT8 Enable
0: Disable
1: Enable

EINT7_CTL

Bit 7
R/W
0x0

External INT7 Enable
0: Disable
1: Enable

EINT6_CTL

Bit 6
R/W
0x0

External INT6 Enable
0: Disable
1: Enable

EINT5_CTL

Bit 5
R/W
0x0

External INT5 Enable
0: Disable
1: Enable

EINT4_CTL

Bit 4
R/W
0x0

External INT4 Enable
0: Disable
1: Enable

EINT3_CTL

Bit 3
R/W
0x0

External INT3 Enable
0: Disable
1: Enable

EINT2_CTL

Bit 2
R/W
0x0

External INT2 Enable
0: Disable
1: Enable

EINT1_CTL

Bit 1
R/W
0x0

External INT1 Enable
0: Disable
1: Enable

EINT0_CTL

Bit 0
R/W
0x0

External INT0 Enable
0: Disable
1: Enable

Bit fields structure

typedef union pc_eint_ctl { struct { unsigned eint0_ctl : 1; unsigned eint1_ctl : 1; unsigned eint2_ctl : 1; unsigned eint3_ctl : 1; unsigned eint4_ctl : 1; unsigned eint5_ctl : 1; unsigned eint6_ctl : 1; unsigned eint7_ctl : 1; unsigned eint8_ctl : 1; unsigned eint9_ctl : 1; unsigned eint10_ctl : 1; unsigned eint11_ctl : 1; unsigned eint12_ctl : 1; unsigned eint13_ctl : 1; unsigned eint14_ctl : 1; unsigned eint15_ctl : 1; unsigned eint16_ctl : 1; unsigned unused0 : 15; } b; unsigned long w; } PC_EINT_CTL