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   ovs-fields    ( 7 )

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REGISTER FIELDS

Summary: Name Bytes Mask RW? Prereqs NXM/OXM Support

───────── ────── ───── ──── ──────── ───────────────────── metadata 8 yes yes none OF 1.2+ and OVS 1.8+ reg0 4 yes yes none OVS 1.1+ reg1 4 yes yes none OVS 1.1+

reg2 4 yes yes none OVS 1.1+ reg3 4 yes yes none OVS 1.1+ reg4 4 yes yes none OVS 1.3+ reg5 4 yes yes none OVS 1.7+

reg6 4 yes yes none OVS 1.7+ reg7 4 yes yes none OVS 1.7+ reg8 4 yes yes none OVS 2.6+ reg9 4 yes yes none OVS 2.6+

reg10 4 yes yes none OVS 2.6+ reg11 4 yes yes none OVS 2.6+ reg12 4 yes yes none OVS 2.6+ reg13 4 yes yes none OVS 2.6+

reg14 4 yes yes none OVS 2.6+ reg15 4 yes yes none OVS 2.6+ xreg0 8 yes yes none OF 1.3+ and OVS 2.4+ xreg1 8 yes yes none OF 1.3+ and OVS 2.4+

xreg2 8 yes yes none OF 1.3+ and OVS 2.4+ xreg3 8 yes yes none OF 1.3+ and OVS 2.4+ xreg4 8 yes yes none OF 1.3+ and OVS 2.4+ xreg5 8 yes yes none OF 1.3+ and OVS 2.4+

xreg6 8 yes yes none OF 1.3+ and OVS 2.4+ xreg7 8 yes yes none OF 1.3+ and OVS 2.4+ xxreg0 16 yes yes none OVS 2.6+ xxreg1 16 yes yes none OVS 2.6+

xxreg2 16 yes yes none OVS 2.6+ xxreg3 16 yes yes none OVS 2.6+

These fields give an OpenFlow switch space for temporary storage while the pipeline is running. Whereas metadata fields can have a meaningful initial value and can persist across some hops across OpenFlow switches, registers are always initially 0 and their values never persist across inter-switch hops (not even across patch ports).

OpenFlow Metadata Field

Name: metadata Width: 64 bits

Format: hexadecimal Masking: arbitrary bitwise masks Prerequisites: none Access: read/write

OpenFlow 1.0: not supported OpenFlow 1.1: yes OXM: OXM_OF_METADATA (2) since OpenFlow 1.2 and Open vSwitch 1.8

NXM: none

This field is the oldest standardized OpenFlow register field, introduced in OpenFlow 1.1. It was introduced to model the limited number of user-defined bits that some ASIC-based switches can carry through their pipelines. Because of hardware limitations, OpenFlow allows switches to support writing and masking only an implementation-defined subset of bits, even no bits at all. The Open vSwitch software switch always supports all 64 bits, but of course an Open vSwitch port to an ASIC would have the same restriction as the ASIC itself.

This field has an OXM code point, but OpenFlow 1.4 and earlier allow it to be modified only with a specialized instruction, not with a ``set-field'' action. OpenFlow 1.5 removes this restriction. Open vSwitch does not enforce this restriction, regardless of OpenFlow version.

Register 0 Field

Name: reg0 Width: 32 bits Format: hexadecimal Masking: arbitrary bitwise masks

Prerequisites: none Access: read/write OpenFlow 1.0: not supported OpenFlow 1.1: not supported

OXM: none NXM: NXM_NX_REG0 (0) since Open vSwitch 1.1

This is the first of several Open vSwitch registers, all of which have the same properties. Open vSwitch 1.1 introduced registers 0, 1, 2, and 3, version 1.3 added register 4, version 1.7 added registers 5, 6, and 7, and version 2.6 added registers 8 through 15.

Extended Register 0 Field

Name: xreg0 Width: 64 bits Format: hexadecimal

Masking: arbitrary bitwise masks Prerequisites: none Access: read/write OpenFlow 1.0: not supported

OpenFlow 1.1: not supported OXM: OXM_OF_PKT_REG0 (0) since OpenFlow 1.3 and Open vSwitch 2.4 NXM: none

This is the first of the registers introduced in OpenFlow 1.5. OpenFlow 1.5 calls these fields just the ``packet registers,'' but Open vSwitch already had 32-bit registers by that name, so Open vSwitch uses the name ``extended registers'' in an attempt to reduce confusion. The standard allows for up to 128 registers, each 64 bits wide, but Open vSwitch only implements 4 (in versions 2.4 and 2.5) or 8 (in version 2.6 and later).

Each of the 64-bit extended registers overlays two of the 32-bit registers: xreg0 overlays reg0 and reg1, with reg0 supplying the most-significant bits of xreg0 and reg1 the least-significant. Similarly, xreg1 overlays reg2 and reg3, and so on.

The OpenFlow specification says, ``In most cases, the packet registers can not be matched in tables, i.e. they usually can not be used in the flow entry match structure'' [OpenFlow 1.5, section 7.2.3.10], but there is no reason for a software switch to impose such a restriction, and Open vSwitch does not.

Double-Extended Register 0 Field

Name: xxreg0 Width: 128 bits Format: hexadecimal

Masking: arbitrary bitwise masks Prerequisites: none Access: read/write OpenFlow 1.0: not supported

OpenFlow 1.1: not supported OXM: none NXM: NXM_NX_XXREG0 (111) since Open vSwitch 2.6

This is the first of the double-extended registers introduce in Open vSwitch 2.6. Each of the 128-bit extended registers overlays four of the 32-bit registers: xxreg0 overlays reg0 through reg3, with reg0 supplying the most-significant bits of xxreg0 and reg3 the least-significant. xxreg1 similarly overlays reg4 through reg7, and so on.