компилятор C и C ++ проекта GNU (GNU project C and C++ compiler)
Параметры подробно (Options detail)
x86 - 1
These -m options are defined for the x86 family of computers.
-march=cpu-type
Generate instructions for the machine type cpu-type. In
contrast to -mtune=cpu-type, which merely tunes the generated
code for the specified cpu-type, -march=cpu-type allows GCC
to generate code that may not run at all on processors other
than the one indicated. Specifying -march=cpu-type implies
-mtune=cpu-type.
The choices for cpu-type are:
native
This selects the CPU to generate code for at compilation
time by determining the processor type of the compiling
machine. Using -march=native enables all instruction
subsets supported by the local machine (hence the result
might not run on different machines). Using
-mtune=native produces code optimized for the local
machine under the constraints of the selected instruction
set.
x86-64
A generic CPU with 64-bit extensions.
i386
Original Intel i386 CPU.
i486
Intel i486 CPU. (No scheduling is implemented for this
chip.)
i586
pentium
Intel Pentium CPU with no MMX support.
lakemont
Intel Lakemont MCU, based on Intel Pentium CPU.
pentium-mmx
Intel Pentium MMX CPU, based on Pentium core with MMX
instruction set support.
pentiumpro
Intel Pentium Pro CPU.
i686
When used with -march, the Pentium Pro instruction set is
used, so the code runs on all i686 family chips. When
used with -mtune, it has the same meaning as generic.
pentium2
Intel Pentium II CPU, based on Pentium Pro core with MMX
instruction set support.
pentium3
pentium3m
Intel Pentium III CPU, based on Pentium Pro core with MMX
and SSE instruction set support.
pentium-m
Intel Pentium M; low-power version of Intel Pentium III
CPU with MMX, SSE and SSE2 instruction set support. Used
by Centrino notebooks.
pentium4
pentium4m
Intel Pentium 4 CPU with MMX, SSE and SSE2 instruction
set support.
prescott
Improved version of Intel Pentium 4 CPU with MMX, SSE,
SSE2 and SSE3 instruction set support.
nocona
Improved version of Intel Pentium 4 CPU with 64-bit
extensions, MMX, SSE, SSE2 and SSE3 instruction set
support.
core2
Intel Core 2 CPU with 64-bit extensions, MMX, SSE, SSE2,
SSE3 and SSSE3 instruction set support.
nehalem
Intel Nehalem CPU with 64-bit extensions, MMX, SSE, SSE2,
SSE3, SSSE3, SSE4.1, SSE4.2 and POPCNT instruction set
support.
westmere
Intel Westmere CPU with 64-bit extensions, MMX, SSE,
SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES and PCLMUL
instruction set support.
sandybridge
Intel Sandy Bridge CPU with 64-bit extensions, MMX, SSE,
SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AES and
PCLMUL instruction set support.
ivybridge
Intel Ivy Bridge CPU with 64-bit extensions, MMX, SSE,
SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AES,
PCLMUL, FSGSBASE, RDRND and F16C instruction set support.
haswell
Intel Haswell CPU with 64-bit extensions, MOVBE, MMX,
SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX,
AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2 and
F16C instruction set support.
broadwell
Intel Broadwell CPU with 64-bit extensions, MOVBE, MMX,
SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX,
AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2, F16C,
RDSEED ADCX and PREFETCHW instruction set support.
skylake
Intel Skylake CPU with 64-bit extensions, MOVBE, MMX,
SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX,
AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2, F16C,
RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC and XSAVES
instruction set support.
bonnell
Intel Bonnell CPU with 64-bit extensions, MOVBE, MMX,
SSE, SSE2, SSE3 and SSSE3 instruction set support.
silvermont
Intel Silvermont CPU with 64-bit extensions, MOVBE, MMX,
SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES,
PREFETCHW, PCLMUL and RDRND instruction set support.
goldmont
Intel Goldmont CPU with 64-bit extensions, MOVBE, MMX,
SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES,
PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES, XSAVEOPT
and FSGSBASE instruction set support.
goldmont-plus
Intel Goldmont Plus CPU with 64-bit extensions, MOVBE,
MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES,
PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES,
XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX and UMIP
instruction set support.
tremont
Intel Tremont CPU with 64-bit extensions, MOVBE, MMX,
SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES,
PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES,
XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, UMIP, GFNI-SSE,
CLWB, MOVDIRI, MOVDIR64B, CLDEMOTE and WAITPKG
instruction set support.
knl Intel Knight's Landing CPU with 64-bit extensions, MOVBE,
MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX,
AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2, F16C,
RDSEED, ADCX, PREFETCHW, PREFETCHWT1, AVX512F, AVX512PF,
AVX512ER and AVX512CD instruction set support.
knm Intel Knights Mill CPU with 64-bit extensions, MOVBE,
MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX,
AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2, F16C,
RDSEED, ADCX, PREFETCHW, PREFETCHWT1, AVX512F, AVX512PF,
AVX512ER, AVX512CD, AVX5124VNNIW, AVX5124FMAPS and
AVX512VPOPCNTDQ instruction set support.
skylake-avx512
Intel Skylake Server CPU with 64-bit extensions, MOVBE,
MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU,
AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2,
F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
XSAVES, AVX512F, CLWB, AVX512VL, AVX512BW, AVX512DQ and
AVX512CD instruction set support.
cannonlake
Intel Cannonlake Server CPU with 64-bit extensions,
MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2,
POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND,
FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW,
CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, AVX512VL, AVX512BW,
AVX512DQ, AVX512CD, AVX512VBMI, AVX512IFMA, SHA and UMIP
instruction set support.
icelake-client
Intel Icelake Client CPU with 64-bit extensions, MOVBE,
MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU,
AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2,
F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD,
AVX512VBMI, AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI,
AVX512VBMI2, AVX512VPOPCNTDQ, AVX512BITALG, AVX512VNNI,
VPCLMULQDQ, VAES instruction set support.
icelake-server
Intel Icelake Server CPU with 64-bit extensions, MOVBE,
MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU,
AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2,
F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD,
AVX512VBMI, AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI,
AVX512VBMI2, AVX512VPOPCNTDQ, AVX512BITALG, AVX512VNNI,
VPCLMULQDQ, VAES, PCONFIG and WBNOINVD instruction set
support.
cascadelake
Intel Cascadelake CPU with 64-bit extensions, MOVBE, MMX,
SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX,
AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2, F16C,
RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES,
AVX512F, CLWB, AVX512VL, AVX512BW, AVX512DQ, AVX512CD and
AVX512VNNI instruction set support.
tigerlake
Intel Tigerlake CPU with 64-bit extensions, MOVBE, MMX,
SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX,
AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2, F16C,
RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES,
AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD,
AVX512VBMI, AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI,
AVX512VBMI2, AVX512VPOPCNTDQ, AVX512BITALG, AVX512VNNI,
VPCLMULQDQ, VAES, PCONFIG, WBNOINVD, MOVDIRI, MOVDIR64B
and CLWB instruction set support.
k6 AMD K6 CPU with MMX instruction set support.
k6-2
k6-3
Improved versions of AMD K6 CPU with MMX and 3DNow!
instruction set support.
athlon
athlon-tbird
AMD Athlon CPU with MMX, 3dNOW!, enhanced 3DNow! and SSE
prefetch instructions support.
athlon-4
athlon-xp
athlon-mp
Improved AMD Athlon CPU with MMX, 3DNow!, enhanced 3DNow!
and full SSE instruction set support.
k8
opteron
athlon64
athlon-fx
Processors based on the AMD K8 core with x86-64
instruction set support, including the AMD Opteron,
Athlon 64, and Athlon 64 FX processors. (This supersets
MMX, SSE, SSE2, 3DNow!, enhanced 3DNow! and 64-bit
instruction set extensions.)
k8-sse3
opteron-sse3
athlon64-sse3
Improved versions of AMD K8 cores with SSE3 instruction
set support.
amdfam10
barcelona
CPUs based on AMD Family 10h cores with x86-64
instruction set support. (This supersets MMX, SSE, SSE2,
SSE3, SSE4A, 3DNow!, enhanced 3DNow!, ABM and 64-bit
instruction set extensions.)
bdver1
CPUs based on AMD Family 15h cores with x86-64
instruction set support. (This supersets FMA4, AVX, XOP,
LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A,
SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set
extensions.)
bdver2
AMD Family 15h core based CPUs with x86-64 instruction
set support. (This supersets BMI, TBM, F16C, FMA, FMA4,
AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3,
SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction
set extensions.)
bdver3
AMD Family 15h core based CPUs with x86-64 instruction
set support. (This supersets BMI, TBM, F16C, FMA, FMA4,
FSGSBASE, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE,
SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit
instruction set extensions.
bdver4
AMD Family 15h core based CPUs with x86-64 instruction
set support. (This supersets BMI, BMI2, TBM, F16C, FMA,
FMA4, FSGSBASE, AVX, AVX2, XOP, LWP, AES, PCL_MUL, CX16,
MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1,
SSE4.2, ABM and 64-bit instruction set extensions.
znver1
AMD Family 17h core based CPUs with x86-64 instruction
set support. (This supersets BMI, BMI2, F16C, FMA,
FSGSBASE, AVX, AVX2, ADCX, RDSEED, MWAITX, SHA, CLZERO,
AES, PCL_MUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A,
SSSE3, SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT,
POPCNT, and 64-bit instruction set extensions.
znver2
AMD Family 17h core based CPUs with x86-64 instruction
set support. (This supersets BMI, BMI2, ,CLWB, F16C, FMA,
FSGSBASE, AVX, AVX2, ADCX, RDSEED, MWAITX, SHA, CLZERO,
AES, PCL_MUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A,
SSSE3, SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT,
POPCNT, and 64-bit instruction set extensions.)
btver1
CPUs based on AMD Family 14h cores with x86-64
instruction set support. (This supersets MMX, SSE, SSE2,
SSE3, SSSE3, SSE4A, CX16, ABM and 64-bit instruction set
extensions.)
btver2
CPUs based on AMD Family 16h cores with x86-64
instruction set support. This includes MOVBE, F16C, BMI,
AVX, PCL_MUL, AES, SSE4.2, SSE4.1, CX16, ABM, SSE4A,
SSSE3, SSE3, SSE2, SSE, MMX and 64-bit instruction set
extensions.
winchip-c6
IDT WinChip C6 CPU, dealt in same way as i486 with
additional MMX instruction set support.
winchip2
IDT WinChip 2 CPU, dealt in same way as i486 with
additional MMX and 3DNow! instruction set support.
c3 VIA C3 CPU with MMX and 3DNow! instruction set support.
(No scheduling is implemented for this chip.)
c3-2
VIA C3-2 (Nehemiah/C5XL) CPU with MMX and SSE instruction
set support. (No scheduling is implemented for this
chip.)
c7 VIA C7 (Esther) CPU with MMX, SSE, SSE2 and SSE3
instruction set support. (No scheduling is implemented
for this chip.)
samuel-2
VIA Eden Samuel 2 CPU with MMX and 3DNow! instruction set
support. (No scheduling is implemented for this chip.)
nehemiah
VIA Eden Nehemiah CPU with MMX and SSE instruction set
support. (No scheduling is implemented for this chip.)
esther
VIA Eden Esther CPU with MMX, SSE, SSE2 and SSE3
instruction set support. (No scheduling is implemented
for this chip.)
eden-x2
VIA Eden X2 CPU with x86-64, MMX, SSE, SSE2 and SSE3
instruction set support. (No scheduling is implemented
for this chip.)
eden-x4
VIA Eden X4 CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2, AVX and AVX2 instruction set support.
(No scheduling is implemented for this chip.)
nano
Generic VIA Nano CPU with x86-64, MMX, SSE, SSE2, SSE3
and SSSE3 instruction set support. (No scheduling is
implemented for this chip.)
nano-1000
VIA Nano 1xxx CPU with x86-64, MMX, SSE, SSE2, SSE3 and
SSSE3 instruction set support. (No scheduling is
implemented for this chip.)
nano-2000
VIA Nano 2xxx CPU with x86-64, MMX, SSE, SSE2, SSE3 and
SSSE3 instruction set support. (No scheduling is
implemented for this chip.)
nano-3000
VIA Nano 3xxx CPU with x86-64, MMX, SSE, SSE2, SSE3,
SSSE3 and SSE4.1 instruction set support. (No scheduling
is implemented for this chip.)
nano-x2
VIA Nano Dual Core CPU with x86-64, MMX, SSE, SSE2, SSE3,
SSSE3 and SSE4.1 instruction set support. (No scheduling
is implemented for this chip.)
nano-x4
VIA Nano Quad Core CPU with x86-64, MMX, SSE, SSE2, SSE3,
SSSE3 and SSE4.1 instruction set support. (No scheduling
is implemented for this chip.)
geode
AMD Geode embedded processor with MMX and 3DNow!
instruction set support.
-mtune=cpu-type
Tune to cpu-type everything applicable about the generated
code, except for the ABI and the set of available
instructions. While picking a specific cpu-type schedules
things appropriately for that particular chip, the compiler
does not generate any code that cannot run on the default
machine type unless you use a -march=cpu-type option. For
example, if GCC is configured for i686-pc-linux-gnu then
-mtune=pentium4 generates code that is tuned for Pentium 4
but still runs on i686 machines.
The choices for cpu-type are the same as for -march. In
addition, -mtune supports 2 extra choices for cpu-type:
generic
Produce code optimized for the most common
IA32/AMD64/EM64T processors. If you know the CPU on
which your code will run, then you should use the
corresponding -mtune or -march option instead of
-mtune=generic. But, if you do not know exactly what CPU
users of your application will have, then you should use
this option.
As new processors are deployed in the marketplace, the
behavior of this option will change. Therefore, if you
upgrade to a newer version of GCC, code generation
controlled by this option will change to reflect the
processors that are most common at the time that version
of GCC is released.
There is no -march=generic option because -march
indicates the instruction set the compiler can use, and
there is no generic instruction set applicable to all
processors. In contrast, -mtune indicates the processor
(or, in this case, collection of processors) for which
the code is optimized.
intel
Produce code optimized for the most current Intel
processors, which are Haswell and Silvermont for this
version of GCC. If you know the CPU on which your code
will run, then you should use the corresponding -mtune or
-march option instead of -mtune=intel. But, if you want
your application performs better on both Haswell and
Silvermont, then you should use this option.
As new Intel processors are deployed in the marketplace,
the behavior of this option will change. Therefore, if
you upgrade to a newer version of GCC, code generation
controlled by this option will change to reflect the most
current Intel processors at the time that version of GCC
is released.
There is no -march=intel option because -march indicates
the instruction set the compiler can use, and there is no
common instruction set applicable to all processors. In
contrast, -mtune indicates the processor (or, in this
case, collection of processors) for which the code is
optimized.
-mcpu=cpu-type
A deprecated synonym for -mtune.
-mfpmath=unit
Generate floating-point arithmetic for selected unit unit.
The choices for unit are:
387 Use the standard 387 floating-point coprocessor present
on the majority of chips and emulated otherwise. Code
compiled with this option runs almost everywhere. The
temporary results are computed in 80-bit precision
instead of the precision specified by the type, resulting
in slightly different results compared to most of other
chips. See -ffloat-store for more detailed description.
This is the default choice for non-Darwin x86-32 targets.
sse Use scalar floating-point instructions present in the SSE
instruction set. This instruction set is supported by
Pentium III and newer chips, and in the AMD line by
Athlon-4, Athlon XP and Athlon MP chips. The earlier
version of the SSE instruction set supports only single-
precision arithmetic, thus the double and extended-
precision arithmetic are still done using 387. A later
version, present only in Pentium 4 and AMD x86-64 chips,
supports double-precision arithmetic too.
For the x86-32 compiler, you must use -march=cpu-type,
-msse or -msse2 switches to enable SSE extensions and
make this option effective. For the x86-64 compiler,
these extensions are enabled by default.
The resulting code should be considerably faster in the
majority of cases and avoid the numerical instability
problems of 387 code, but may break some existing code
that expects temporaries to be 80 bits.
This is the default choice for the x86-64 compiler,
Darwin x86-32 targets, and the default choice for x86-32
targets with the SSE2 instruction set when -ffast-math is
enabled.
sse,387
sse+387
both
Attempt to utilize both instruction sets at once. This
effectively doubles the amount of available registers,
and on chips with separate execution units for 387 and
SSE the execution resources too. Use this option with
care, as it is still experimental, because the GCC
register allocator does not model separate functional
units well, resulting in unstable performance.
-masm=dialect
Output assembly instructions using selected dialect. Also
affects which dialect is used for basic "asm" and extended
"asm". Supported choices (in dialect order) are att or intel.
The default is att. Darwin does not support intel.
-mieee-fp
-mno-ieee-fp
Control whether or not the compiler uses IEEE floating-point
comparisons. These correctly handle the case where the
result of a comparison is unordered.
-m80387
-mhard-float
Generate output containing 80387 instructions for floating
point.
-mno-80387
-msoft-float
Generate output containing library calls for floating point.
Warning: the requisite libraries are not part of GCC.
Normally the facilities of the machine's usual C compiler are
used, but this cannot be done directly in cross-compilation.
You must make your own arrangements to provide suitable
library functions for cross-compilation.
On machines where a function returns floating-point results
in the 80387 register stack, some floating-point opcodes may
be emitted even if -msoft-float is used.
-mno-fp-ret-in-387
Do not use the FPU registers for return values of functions.
The usual calling convention has functions return values of
types "float" and "double" in an FPU register, even if there
is no FPU. The idea is that the operating system should
emulate an FPU.
The option -mno-fp-ret-in-387 causes such values to be
returned in ordinary CPU registers instead.
-mno-fancy-math-387
Some 387 emulators do not support the "sin", "cos" and "sqrt"
instructions for the 387. Specify this option to avoid
generating those instructions. This option is overridden
when -march indicates that the target CPU always has an FPU
and so the instruction does not need emulation. These
instructions are not generated unless you also use the
-funsafe-math-optimizations switch.
-malign-double
-mno-align-double
Control whether GCC aligns "double", "long double", and "long
long" variables on a two-word boundary or a one-word
boundary. Aligning "double" variables on a two-word boundary
produces code that runs somewhat faster on a Pentium at the
expense of more memory.
On x86-64, -malign-double is enabled by default.
Warning: if you use the -malign-double switch, structures
containing the above types are aligned differently than the
published application binary interface specifications for the
x86-32 and are not binary compatible with structures in code
compiled without that switch.
-m96bit-long-double
-m128bit-long-double
These switches control the size of "long double" type. The
x86-32 application binary interface specifies the size to be
96 bits, so -m96bit-long-double is the default in 32-bit
mode.
Modern architectures (Pentium and newer) prefer "long double"
to be aligned to an 8- or 16-byte boundary. In arrays or
structures conforming to the ABI, this is not possible. So
specifying -m128bit-long-double aligns "long double" to a
16-byte boundary by padding the "long double" with an
additional 32-bit zero.
In the x86-64 compiler, -m128bit-long-double is the default
choice as its ABI specifies that "long double" is aligned on
16-byte boundary.
Notice that neither of these options enable any extra
precision over the x87 standard of 80 bits for a "long
double".
Warning: if you override the default value for your target
ABI, this changes the size of structures and arrays
containing "long double" variables, as well as modifying the
function calling convention for functions taking "long
double". Hence they are not binary-compatible with code
compiled without that switch.
-mlong-double-64
-mlong-double-80
-mlong-double-128
These switches control the size of "long double" type. A size
of 64 bits makes the "long double" type equivalent to the
"double" type. This is the default for 32-bit Bionic C
library. A size of 128 bits makes the "long double" type
equivalent to the "__float128" type. This is the default for
64-bit Bionic C library.
Warning: if you override the default value for your target
ABI, this changes the size of structures and arrays
containing "long double" variables, as well as modifying the
function calling convention for functions taking "long
double". Hence they are not binary-compatible with code
compiled without that switch.
-malign-data=type
Control how GCC aligns variables. Supported values for type
are compat uses increased alignment value compatible uses GCC
4.8 and earlier, abi uses alignment value as specified by the
psABI, and cacheline uses increased alignment value to match
the cache line size. compat is the default.
-mlarge-data-threshold=threshold
When -mcmodel=medium is specified, data objects larger than
threshold are placed in the large data section. This value
must be the same across all objects linked into the binary,
and defaults to 65535.
-mrtd
Use a different function-calling convention, in which
functions that take a fixed number of arguments return with
the "ret num" instruction, which pops their arguments while
returning. This saves one instruction in the caller since
there is no need to pop the arguments there.
You can specify that an individual function is called with
this calling sequence with the function attribute "stdcall".
You can also override the -mrtd option by using the function
attribute "cdecl".
Warning: this calling convention is incompatible with the one
normally used on Unix, so you cannot use it if you need to
call libraries compiled with the Unix compiler.
Also, you must provide function prototypes for all functions
that take variable numbers of arguments (including "printf");
otherwise incorrect code is generated for calls to those
functions.
In addition, seriously incorrect code results if you call a
function with too many arguments. (Normally, extra arguments
are harmlessly ignored.)
-mregparm=num
Control how many registers are used to pass integer
arguments. By default, no registers are used to pass
arguments, and at most 3 registers can be used. You can
control this behavior for a specific function by using the
function attribute "regparm".
Warning: if you use this switch, and num is nonzero, then you
must build all modules with the same value, including any
libraries. This includes the system libraries and startup
modules.
-msseregparm
Use SSE register passing conventions for float and double
arguments and return values. You can control this behavior
for a specific function by using the function attribute
"sseregparm".
Warning: if you use this switch then you must build all
modules with the same value, including any libraries. This
includes the system libraries and startup modules.
-mvect8-ret-in-mem
Return 8-byte vectors in memory instead of MMX registers.
This is the default on Solaris 8 and 9 and VxWorks to match
the ABI of the Sun Studio compilers until version 12. Later
compiler versions (starting with Studio 12 Update 1) follow
the ABI used by other x86 targets, which is the default on
Solaris 10 and later. Only use this option if you need to
remain compatible with existing code produced by those
previous compiler versions or older versions of GCC.
