Регистры H616: PLL_CPUX Control Register

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

PLL_ENABLE

Bit 31
R/W
0x0

0: Disable
1: Enable
PLL_CPUX=24 MHz*N/P
The PLL_CPUX output frequency must be in the range from 200 MHz to 3
GHz. And the default value of PLL_CPUX is 408 MHz.

Unused

Bit 30

LOCK_ENABLE

Bit 29
R/W
0x0

Lock Enable
0: Disable
1: Enable

LOCK

Bit 28
R
0x0

0:Unlocked
1: Locked (It indicates that the PLL has been stable.)

PLL_OUTPUT_ENABLE

Bit 27
R/W
0x1

0:Disable
1:Enable
The bit is used to control the output enable of PLL.

PLL_LOCK_TIME

Bits 26 : 24
R/W
0x0

PLL lock time
The bit indicates the step amplitude from one frequency to another.

Unused

Bits 23 : 18

PLL_OUT_EXT_DIVP

Bits 17 : 16
R/W
0x0

PLL Output External Divider P

00: 1
01: 2
10: 4
11: /
When output clock is less than 288 MHz, clock frequency is output by
dividing P.

PLL_FACTOR_N

Bits 15 : 8
R/W
0x10

PLL Factor N
N = PLL_FACTOR_N +1
PLL_FACTOR_N is from 0 to 254.
In application, PLL_FACTOR_N shall be more than or equal to 11.

Unused

Bits 7 : 2

PLL_FACTOR_M

Bits 1 : 0
R/W
0x0

PLL Factor M
M = PLL_FACTOR_M + 1
PLL_FACTOR_M is from 0 to 3.
Note: The bit is only for testing.

Bit fields structure

typedef union pll_cpux_ctrl_reg { struct { unsigned pll_factor_m : 2; unsigned unused0 : 6; unsigned pll_factor_n : 8; unsigned pll_out_ext_divp : 2; unsigned unused1 : 6; unsigned pll_lock_time : 3; unsigned pll_output_enable : 1; unsigned lock : 1; unsigned lock_enable : 1; unsigned unused2 : 1; unsigned pll_enable : 1; } b; unsigned long w; } PLL_CPUX_CTRL_REG