Регистры H616: PLL_VIDEO0 Control Register

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

PLL_ENABLE

Bit 31
R/W
0x0

0: Disable
1: Enable
For application,
PLL_VIDEO0(4X)= 24 MHz*N/M.
PLL_VIDEO0(1X)=24 MHz*N/M/4.
The default value of PLL_VIDEO0(4X) is 1188 MHz.

Unused

Bit 30

LOCK_ENABLE

Bit 29
R/W
0x0

Lock Enable
0: Disable
1: Enable

LOCK

Bit 28
R
0x0

0:Unlocked
1: Locked (It indicates that the PLL has been stable.)

PLL_OUTPUT_ENABLE

Bit 27
R/W
0x1

0: Disable
1: Enable
The bit is used to control the output enable of PLL.

Unused

Bits 26 : 25

PLL_SDM_ENABLE

Bit 24
R/W
0x0

0: Disable
1: Enable

Unused

Bits 23 : 16

PLL_FACTOR_N

Bits 15 : 8
R/W
0x62

PLL Factor N
N= PLL_FACTOR_N +1
PLL_FACTOR_N is from 0 to 254.
In application, PLL_FACTOR_N shall be more than or equal to 11.

Unused

Bits 7 : 2

PLL_INPUT_DIV_M

Bit 1
R/W
0x1

PLL Input Div M
M1=PLL_INPUT_DIV_M + 1
PLL_INPUT_DIV_M is from 0 to 1.

PLL_OUTPUT_DIV_D

Bit 0
R/W
0x1

PLL Output Div D
M0=PLL_OUTPUT_DIV_D + 1
PLL_OUTPUT_DIV_D is from 0 to 1.
The bit is only for testing.
For test, PLL_VIDEO0(4X) =24 MHz*N/M/D

Bit fields structure

typedef union pll_video0_ctrl_reg { struct { unsigned pll_output_div_d : 1; unsigned pll_input_div_m : 1; unsigned unused0 : 6; unsigned pll_factor_n : 8; unsigned unused1 : 8; unsigned pll_sdm_enable : 1; unsigned unused2 : 2; unsigned pll_output_enable : 1; unsigned lock : 1; unsigned lock_enable : 1; unsigned unused3 : 1; unsigned pll_enable : 1; } b; unsigned long w; } PLL_VIDEO0_CTRL_REG