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PLL_AUDIO_CTRL_REG
3.3.4. PLL_AUDIO Control Register - адрес: 0x3001078 (смещение: 0x0078)

Контроллер синхрогенератора: список регистров

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

  PLL_ENABLE

Bit 31
R/W
0x0

0: Disable
1: Enable
This PLL is for Audio.
PLL_AUDIO(hs)=24 MHz*N/M1
PLL_AUDIO(4X) = 24 MHz*N/M0/M1/P
PLL_AUDIO(2X) = 24 MHz*N/M0/M1/P/2
PLL_AUDIO(1X) = 24 MHz*N/M0/M1/P/4


7.5 ≤ N/M0/M1 ≤ 125 and 12 ≤ N

The range of 24 MHz*N/M0/M1 is from 180 MHz to 3 GHz.
The default value of PLL_AUDIO(4X) is 24.5714 MHz.
Common configuration:
When PLL_AUDIO(1X) is 24.576 MHz, PLL_AUDIO_CTRL_REG is
recommended to set to 0xA8010F01, PLL_AUDIO_PAR0_CTRL_REG is
recommended to set to 0xE000C49B.
When PLL_AUDIO(1X) is 22.5792 MHz, PLL_AUDIO_CTRL_REG is
recommended to set to 0xA8021501, PLL_AUDIO_PAR0_CTRL_REG is
recommended to set to 0xE001288C.

  Unused

Bit 30

  LOCK_ENABLE

Bit 29
R/W
0x0

Lock Enable
0: Disable
1: Enable

  LOCK

Bit 28
R
0x0

0:Unlocked
1: Locked (It indicates that the PLL has been stable.)
Note: The bit is only valid when the bit29 is set to 1.

  PLL_OUTPUT_ENABLE

Bit 27
R/W
0x1

0:Disable
1:Enable
The bit is used to control the output enable of PLL.

  Unused

Bits 26 : 25

  PLL_SDM_ENABLE

Bit 24
R/W
0x0

Spread Spectrum and Decimal Frequency Division
0: Disable
1: Enable

  Unused

Bits 23 : 22

  PLL_POST_DIV_P

Bits 21 : 16
R/W
0x14

PLL Post-div P
P= PLL_POST_DIV_P +1
PLL_POST_DIV_P is from 0 to 63.

  PLL_FACTOR_N

Bits 15 : 8
R/W
0x2A

PLL Factor N
N= PLL_FACTOR_N +1
PLL_FACTOR_N is from 0 to 254.
In application, PLL_FACTOR_N shall be more than or equal to 11.

  Unused

Bits 7 : 2

  PLL_INPUT_DIV_M1

Bit 1
R/W
0x0

PLL Input Div M1
M1=PLL_INPUT_DIV_M1 + 1
PLL_INPUT_DIV_M1 is from 0 to 1.

  PLL_OUTPUT_DIV_M0

Bit 0
R/W
0x1

PLL Output Div M0
M0=PLL_OUTPUT_DIV_M0 + 1
PLL_OUTPUT_DIV_M0 is from 0 to 1.

Команда U-Boot для чтения регистра

md 3001078 1

Bit fields structure 

typedef union  pll_audio_ctrl_reg
{
  struct
  {
   unsigned pll_output_div_m0 : 1;
   unsigned pll_input_div_m1 : 1;
   unsigned unused0 : 6;
   unsigned pll_factor_n : 8;
   unsigned pll_post_div_p : 6;
   unsigned unused1 : 2;
   unsigned pll_sdm_enable : 1;
   unsigned unused2 : 2;
   unsigned pll_output_enable : 1;
   unsigned lock : 1;
   unsigned lock_enable : 1;
   unsigned unused3 : 1;
   unsigned pll_enable : 1;
  } b;
   unsigned long w;
} PLL_AUDIO_CTRL_REG
Allwinner H616 Manual