Регистры H616: PLL_DDR0 Pattern Control Register

PLL_DDR0_PAT_CTRL_REG

3.3.4. PLL_DDR0 Pattern Control Register - адрес: 0x3001110 (смещение: 0x0110)

Контроллер синхрогенератора: список регистров

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

SIG_DELT_PAT_EN

Bit 31
R/W
0x0

Sigma-Delta Pattern Enable

SPR_FREQ_MODE

Bits 30 : 29
R/W
0x0

Spread Frequency Mode
00: DC=0
01: DC=1
10: Triangular(1bit)
11: Triangular(nbit)

WAVE_STEP

Bits 28 : 20
R/W
0x0

Wave Step

SDM_CLK_SEL

Bit 19
R/W
0x0

0: 24 MHz
1: 12 MHz
SDM Clock Select
When PLL_INPUT_DIV_M1 is 1, the bit is set to 1.

FREQ

Bits 18 : 17
R/W
0x0

Frequency
00: 31.5 kHz
01: 32 kHz
10: 32.5 kHz
11: 33 kHz

WAVE_BOT

Bits 16 : 0
R/W
0x0

Wave Bottom

Bit fields structure

typedef union pll_ddr0_pat_ctrl_reg { struct { unsigned wave_bot : 17; unsigned freq : 2; unsigned sdm_clk_sel : 1; unsigned wave_step : 9; unsigned spr_freq_mode : 2; unsigned sig_delt_pat_en : 1; } b; unsigned long w; } PLL_DDR0_PAT_CTRL_REG