Регистры H616: GPU Clock0 Register

GPU_CLK0_REG

3.3.4. GPU Clock0 Register - адрес: 0x3001670 (смещение: 0x0670)

Контроллер синхрогенератора: список регистров

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

SCLK_GATING

Bit 31
R/W
0x0

Gating Special Clock
0: Clock is OFF
1: Clock is ON
SCLK = Clock Source/M.

Unused

Bits 30 : 25

CLK_SRC_SEL

Bit 24
R/W
0x0

Clock Source Select
0: PLL_GPU0
1: PLL_PERI_BAK_CLK(PLL_PERI_BAK_CLK is from GPU_CLK1_REG)
Note: The switch needs to be a burr-free switch.

Unused

Bits 23 : 2

FACTOR_M

Bits 1 : 0
R/W
0x0

Factor M.(M= FACTOR_M +1)
FACTOR_M is from 0 to 3.
Burr-free divider.

Bit fields structure

typedef union gpu_clk0_reg { struct { unsigned factor_m : 2; unsigned unused0 : 22; unsigned clk_src_sel : 1; unsigned unused1 : 6; unsigned sclk_gating : 1; } b; unsigned long w; } GPU_CLK0_REG