Регистры H616: MBUS Master Clock Gating Register

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

Unused

Bits 31 : 11

G2D_MCLK_GATING

Bit 10
R/W
0x0

Gating MBUS Clock For G2D
0: Mask
1: Pass

Unused

Bit 9

RESERV

Bit 8
R/W
0x0

Reserved

Unused

Bits 7 : 6

NAND0_MCLK_GATING

Bit 5
R/W
0x0

Gating MBUS Clock For NAND0
0: Mask
1: Pass

Unused

Bit 4

TS0_MCLK_GATING

Bit 3
R/W
0x0

Gating MBUS Clock For TS0
0: Mask
1: Pass

CE_MCLK_GATING

Bit 2
R/W
0x0

Gating MBUS Clock For CE
0: Mask
1: Pass

VE_MCLK_GATING

Bit 1
R/W
0x0

Gating MBUS Clock For VE
0: Mask
1: Pass

DMA_MCLK_GATING

Bit 0
R/W
0x0

Gating MBUS Clock For DMA
0: Mask
1: Pass

Note
DE MCLK is put in DE module to control. DI MCLK is put in DI module to control.

Bit fields structure

typedef union mbus_mat_clk_gating_reg { struct { unsigned dma_mclk_gating : 1; unsigned ve_mclk_gating : 1; unsigned ce_mclk_gating : 1; unsigned ts0_mclk_gating : 1; unsigned unused0 : 1; unsigned nand0_mclk_gating : 1; unsigned unused1 : 2; unsigned reserv : 1; unsigned unused2 : 1; unsigned g2d_mclk_gating : 1; unsigned unused3 : 21; } b; unsigned long w; } MBUS_MAT_CLK_GATING_REG