Регистры H616: UART Bus Gating Reset Register

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

Unused

Bits 31 : 22

UART5_RST

Bit 21
R/W
0x0

UART5 Reset
0: Assert
1: De-assert

UART4_RST

Bit 20
R/W
0x0

UART4 Reset
0: Assert
1: De-assert

UART3_RST

Bit 19
R/W
0x0

UART3 Reset
0: Assert
1: De-assert

UART2_RST

Bit 18
R/W
0x0

UART2 Reset
0: Assert
1: De-assert

UART1_RST

Bit 17
R/W
0x0

UART1 Reset
0: Assert
1: De-assert

UART0_RST

Bit 16
R/W
0x0

UART0 Reset
0: Assert
1: De-assert

Unused

Bits 15 : 6

UART5_GATING

Bit 5
R/W
0x0

Gating Clock for UART5
0: Mask
1: Pass

UART4_GATING

Bit 4
R/W
0x0

Gating Clock for UART4
0: Mask
1: Pass

UART3_GATING

Bit 3
R/W
0x0

Gating Clock for UART3
0: Mask
1: Pass

UART2_GATING

Bit 2
R/W
0x0

Gating Clock for UART2
0: Mask
1: Pass

UART1_GATING

Bit 1
R/W
0x0

Gating Clock for UART1
0: Mask
1: Pass

UART0_GATING

Bit 0
R/W
0x0

Gating Clock for UART0
0: Mask
1: Pass

Note
The working clock of UART is APB2.

Bit fields structure

typedef union uart_bgr_reg { struct { unsigned uart0_gating : 1; unsigned uart1_gating : 1; unsigned uart2_gating : 1; unsigned uart3_gating : 1; unsigned uart4_gating : 1; unsigned uart5_gating : 1; unsigned unused0 : 10; unsigned uart0_rst : 1; unsigned uart1_rst : 1; unsigned uart2_rst : 1; unsigned uart3_rst : 1; unsigned uart4_rst : 1; unsigned uart5_rst : 1; unsigned unused1 : 10; } b; unsigned long w; } UART_BGR_REG