Регистры H616: DMIC Clock Register

DMIC_CLK_REG

3.3.4. DMIC Clock Register - адрес: 0x3001a40 (смещение: 0x0A40)

Контроллер синхрогенератора: список регистров

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

SCLK_GATING

Bit 31
R/W
0x0

Gating Special Clock
0: Clock is OFF
1: Clock is ON
SCLK = Clock Source/N

Unused

Bits 30 : 26

CLK_SRC_SEL

Bits 25 : 24
R/W
0x0

Clock Source Select
00: PLL_AUDIO(1X)
01: PLL_AUDIO(2X)
10: PLL_AUDIO(4X)
11: PLL_AUDIO(hs)

Unused

Bits 23 : 10

FACTOR_N

Bits 9 : 8
R/W
0x0

Factor N
00: 1
01: 2
10: 4
11: 8

Unused

Bits 7 : 0

Bit fields structure

typedef union dmic_clk_reg { struct { unsigned unused0 : 8; unsigned factor_n : 2; unsigned unused1 : 14; unsigned clk_src_sel : 2; unsigned unused2 : 5; unsigned sclk_gating : 1; } b; unsigned long w; } DMIC_CLK_REG