Регистры H616: USB0 Clock Register

USB0_CLK_REG

3.3.4. USB0 Clock Register - адрес: 0x3001a70 (смещение: 0x0A70)

Контроллер синхрогенератора: список регистров

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

SCLK_GATING_OHCI0

Bit 31
R/W
0x0

Gating Special Clock For OHCI0
0: Clock is OFF
1: Clock is ON

USBPHY0_RST

Bit 30
R/W
0x0

USB PHY0 Reset
0: Assert
1: De-assert

SCLK_GATING_USBPHY0

Bit 29
R/W
0x0

Gating Special Clock For USBPHY0
0: Clock is OFF
1: Clock is ON
SCLK is from OSC24M.

Unused

Bits 28 : 26

OHCI0_12M_SRC_SEL

Bits 25 : 24
R/W
0x0

OHCI0 12M Source Select
00: 12M divided from 48 MHz
01: 12M divided from 24 MHz
10: LOSC
11: /

Unused

Bits 23 : 0

Bit fields structure

typedef union usb0_clk_reg { struct { unsigned unused0 : 24; unsigned ohci0_12m_src_sel : 2; unsigned unused1 : 3; unsigned sclk_gating_usbphy0 : 1; unsigned usbphy0_rst : 1; unsigned sclk_gating_ohci0 : 1; } b; unsigned long w; } USB0_CLK_REG