Регистры H616: HDMI0 Clock Register

HDMI0_CLK_REG

3.3.4. HDMI0 Clock Register - адрес: 0x3001b00 (смещение: 0x0B00)

Контроллер синхрогенератора: список регистров

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

SCLK_GATING

Bit 31
R/W
0x0

Gating Special Clock
0: Clock is OFF
1: Clock is ON
SCLK = Clock Source/M.

Unused

Bits 30 : 26

CLK_SRC_SEL

Bits 25 : 24
R/W
0x0

Clock Source Select
00: PLL_VIDEO0(1X)
01: PLL_VIDEO0(4X)
10:PLL_VIDEO2(1X)
11:PLL_VIDEO2(4X)

Unused

Bits 23 : 4

FACTOR_M

Bits 3 : 0
R/W
0x0

Factor M.(M= FACTOR_M +1)
FACTOR_M is from 0 to 15.

Bit fields structure

typedef union hdmi0_clk_reg { struct { unsigned factor_m : 4; unsigned unused0 : 20; unsigned clk_src_sel : 2; unsigned unused1 : 5; unsigned sclk_gating : 1; } b; unsigned long w; } HDMI0_CLK_REG