Регистры H616: TCON TV1 Clock Register

TCON_TV1_CLK_REG

3.3.4. TCON TV1 Clock Register - адрес: 0x3001b80 (смещение: 0x0B80)

Контроллер синхрогенератора: список регистров

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

SCLK_GATING

Bit 31
R/W
0x0

Gating Special Clock
0: Clock is OFF
1: Clock is ON
SCLK = Clock Source/M/N.

Unused

Bits 30 : 27

CLK_SRC_SEL

Bits 26 : 24
R/W
0x0

Clock Source Select
000: PLL_VIDEO0(1X)
001: PLL_VIDEO0(4X)
010: PLL_VIDEO1(1X)
011: PLL_VIDEO1(4X)
100: /
101: /

Unused

Bits 23 : 10

FACTOR_N

Bits 9 : 8
R/W
0x0

Factor N
00: 1
01: 2
10: 4
11: 8

Unused

Bits 7 : 4

FACTOR_M

Bits 3 : 0
R/W
0x0

Factor M.(M= FACTOR_M +1)
FACTOR_M is from 0 to 15.

Bit fields structure

typedef union tcon_tv1_clk_reg { struct { unsigned factor_m : 4; unsigned unused0 : 4; unsigned factor_n : 2; unsigned unused1 : 14; unsigned clk_src_sel : 3; unsigned unused2 : 4; unsigned sclk_gating : 1; } b; unsigned long w; } TCON_TV1_CLK_REG