Регистры H616: PLL Lock Debug Control Register

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

DBG_EN

Bit 31
R/W
0x0

Debug Enable
0: Disable
1: Enable

Unused

Bits 30 : 25

DBG_SEL

Bits 24 : 20
R/W
0x0

Debug Select
00000: PLL_C0_CPUX
00001: /
00010: PLL_DDR0
00011: PLL_DDR1
00100: PLL_PERI0
00101: PLL_PERI1
00110: PLL_GPU
00111: /
01000: PLL_VIDEO0
01001: PLL_VIDEO1
01010: /
01011: PLL_VE
01100: PLL_DE
01101: /
01110: /
01111: PLL_AUDIO
10000: /
10001: /
10010: /
10011: /
10100: /
10101: /
10110: /
10111: /
11000: /
11001: /
11010: /
11011: /
11100: /
Others: /

Unused

Bit 19

UNLOCK_LEVEL

Bits 18 : 17
R/W
0x0

Unlock Level
00: 21-29 Clock Cycles
01: 22-28 Clock Cycles
1X: 20-30 Clock Cycles

LOCK_LEVEL

Bit 16
R/W
0x0

Lock Level
0: 24-26 Clock Cycles
1: 23-27 Clock Cycles

Unused

Bits 15 : 0

Bit fields structure

typedef union pll_lock_dbg_ctrl_reg { struct { unsigned unused0 : 16; unsigned lock_level : 1; unsigned unlock_level : 2; unsigned unused1 : 1; unsigned dbg_sel : 5; unsigned unused2 : 6; unsigned dbg_en : 1; } b; unsigned long w; } PLL_LOCK_DBG_CTRL_REG