Регистры H616: 24M or 27M Clock Output Regist

24M_27M_CLK_OUTPUT_REG

3.3.4. 24M or 27M Clock Output Regist - адрес: 0x3001f20 (смещение: 0x0F20)

Контроллер синхрогенератора: список регистров

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

27M_CLK_OUTPUT_EN

Bit 31
R/W
0x0

27M Clock Output enable
0: Disable
1: Enable

24M_27M_SEL

Bit 30
R/w
0x0

0:27M
1:24M
When selecting 24M, the clock is from crystal.
When selecting 27M, the clock is from PLL_CSI, if div_sel is valid, 27M clock
can be output by configuring PLL_CSI and div_sel.

Unused

Bits 29 : 2

DIV_SEL

Bits 1 : 0
R/W
0x0

00:Div2
01:Div4
10:Div8
11:Div16
Only for 27M clock.

Bit fields structure

typedef union 24m_27m_clk_output_reg { struct { unsigned div_sel : 2; unsigned unused0 : 28; unsigned 24m_27m_sel : 1; unsigned 27m_clk_output_en : 1; } b; unsigned long w; } 24M_27M_CLK_OUTPUT_REG