Регистры H616: Модуль управления памятью ввода-вывода IOMMU

Регистров: 113

Имя регистра | Смещение

typedef union iommu_reset_reg { struct { unsigned master0_reset : 1; unsigned master1_reset : 1; unsigned master2_reset : 1; unsigned master3_reset : 1; unsigned master4_reset : 1; unsigned master5_reset : 1; unsigned master6_reset : 1; unsigned unused0 : 9; unsigned macro_tlb_reset : 1; unsigned ptw_cache_reset : 1; unsigned unused1 : 13; unsigned iommu_reset : 1; } b; unsigned long w; } IOMMU_RESET_REG

2) IOMMU_ENABLE_REG | 0x0020

typedef union iommu_enable_reg { struct { unsigned enable : 1; unsigned unused0 : 31; } b; unsigned long w; } IOMMU_ENABLE_REG

3) IOMMU_BYPASS_REG | 0x0030

typedef union iommu_bypass_reg { struct { unsigned master0_bypass : 1; unsigned master1_bypass : 1; unsigned master2_bypass : 1; unsigned master3_bypass : 1; unsigned master4_bypass : 1; unsigned master5_bypass : 1; unsigned master6_bypass : 1; unsigned unused0 : 25; } b; unsigned long w; } IOMMU_BYPASS_REG

4) IOMMU_AUTO_GATING_REG | 0x0040

typedef union iommu_auto_gating_reg { struct { unsigned iommu_auto_gating : 1; unsigned unused0 : 31; } b; unsigned long w; } IOMMU_AUTO_GATING_REG

5) IOMMU_WBUF_CTRL_REG | 0x0044

typedef union iommu_wbuf_ctrl_reg { struct { unsigned master0_wbuf_ctrl : 1; unsigned unused0 : 2; unsigned master3_wbuf_ctrl : 1; unsigned master4_wbuf_ctrl : 1; unsigned master5_wbuf_ctrl : 1; unsigned unused1 : 26; } b; unsigned long w; } IOMMU_WBUF_CTRL_REG

6) IOMMU_OOO_CTRL_REG | 0x0048

typedef union iommu_ooo_ctrl_reg { struct { unsigned master0_ooo_ctrl : 1; unsigned master1_ooo_ctrl : 1; unsigned master2_ooo_ctrl : 1; unsigned master3_ooo_ctrl : 1; unsigned master4_ooo_ctrl : 1; unsigned master5_ooo_ctrl : 1; unsigned master6_ooo_ctrl : 1; unsigned unused0 : 25; } b; unsigned long w; } IOMMU_OOO_CTRL_REG

7) IOMMU_4KB_BDY_PRT_CTRL_REG | 0x004C

typedef union iommu_4kb_bdy_prt_ctrl_reg { struct { unsigned master0_4kb_bdy_prt_ctrl : 1; unsigned master1_4kb_bdy_prt_ctrl : 1; unsigned master2_4kb_bdy_prt_ctrl : 1; unsigned master3_4kb_bdy_prt_ctrl : 1; unsigned master4_4kb_bdy_prt_ctrl : 1; unsigned master5_4kb_bdy_prt_ctrl : 1; unsigned master6_4kb_bdy_prt_ctrl : 1; unsigned unused0 : 25; } b; unsigned long w; } IOMMU_4KB_BDY_PRT_CTRL_REG

8) IOMMU_TTB_REG | 0x0050

typedef union iommu_ttb_reg { struct { unsigned unused0 : 14; unsigned ttb : 18; } b; unsigned long w; } IOMMU_TTB_REG

9) IOMMU_TLB_ENABLE_REG | 0x0060

typedef union iommu_tlb_enable_reg { struct { unsigned micro_tlb0_enable : 1; unsigned micro_tlb1_enable : 1; unsigned micro_tlb2_enable : 1; unsigned micro_tlb3_enable : 1; unsigned micro_tlb4_enable : 1; unsigned micro_tlb5_enable : 1; unsigned micro_tlb6_enable : 1; unsigned unused0 : 9; unsigned macro_tlb_enable : 1; unsigned ptw_cache_enable : 1; unsigned unused1 : 14; } b; unsigned long w; } IOMMU_TLB_ENABLE_REG

10) IOMMU_TLB_PREFETCH_REG | 0x0070

typedef union iommu_tlb_prefetch_reg { struct { unsigned micro_tlb0_prefetch : 1; unsigned micro_tlb1_prefetch : 1; unsigned micro_tlb2_prefetch : 1; unsigned micro_tlb3_prefetch : 1; unsigned micro_tlb4_prefetch : 1; unsigned micro_tlb5_prefetch : 1; unsigned micro_tlb6_prefetch : 1; unsigned unused0 : 25; } b; unsigned long w; } IOMMU_TLB_PREFETCH_REG

11) IOMMU_TLB_FLUSH_ENABLE_REG | 0x0080

typedef union iommu_tlb_flush_enable_reg { struct { unsigned micro_tlb0_flush : 1; unsigned micro_tlb1_flush : 1; unsigned micro_tlb2_flush : 1; unsigned micro_tlb3_flush : 1; unsigned micro_tlb4_flush : 1; unsigned micro_tlb5_flush : 1; unsigned micro_tlb6_flush : 1; unsigned unused0 : 9; unsigned macro_tlb_flush : 1; unsigned ptw_cache_flush : 1; unsigned unused1 : 14; } b; unsigned long w; } IOMMU_TLB_FLUSH_ENABLE_REG

12) IOMMU_TLB_IVLD_MODE_SEL_REG | 0x0084

typedef union iommu_tlb_ivld_mode_sel_reg { struct { unsigned tlb_ivld_mode_sel : 1; unsigned unused0 : 31; } b; unsigned long w; } IOMMU_TLB_IVLD_MODE_SEL_REG

13) IOMMU_TLB_IVLD_STA_ADDR_REG | 0x0088

typedef union iommu_tlb_ivld_sta_addr_reg { struct { unsigned unused0 : 12; unsigned tlb_ivld_sta_addr : 20; } b; unsigned long w; } IOMMU_TLB_IVLD_STA_ADDR_REG

14) IOMMU_TLB_IVLD_END_ADDR_REG | 0x008C

typedef union iommu_tlb_ivld_end_addr_reg { struct { unsigned unused0 : 12; unsigned tlb_ivld_end_addr : 20; } b; unsigned long w; } IOMMU_TLB_IVLD_END_ADDR_REG

15) IOMMU_TLB_IVLD_ADDR_REG | 0x0090

typedef union iommu_tlb_ivld_addr_reg { struct { unsigned unused0 : 12; unsigned tlb_ivld_addr : 20; } b; unsigned long w; } IOMMU_TLB_IVLD_ADDR_REG

16) IOMMU_TLB_IVLD_ADDR_MASK_REG | 0x0094

typedef union iommu_tlb_ivld_addr_mask_reg { struct { unsigned unused0 : 12; unsigned tlb_ivld_addr_mask : 20; } b; unsigned long w; } IOMMU_TLB_IVLD_ADDR_MASK_REG

17) IOMMU_TLB_IVLD_ENABLE_REG | 0x0098

typedef union iommu_tlb_ivld_enable_reg { struct { unsigned tlb_ivld_enable : 1; unsigned unused0 : 31; } b; unsigned long w; } IOMMU_TLB_IVLD_ENABLE_REG

18) IOMMU_PC_IVLD_ADDR_REG | 0x00A0

typedef union iommu_pc_ivld_addr_reg { struct { unsigned unused0 : 20; unsigned pc_ivld_addr : 12; } b; unsigned long w; } IOMMU_PC_IVLD_ADDR_REG

19) IOMMU_PC_IVLD_ENABLE_REG | 0x00A8

typedef union iommu_pc_ivld_enable_reg { struct { unsigned pc_ivld_enable : 1; unsigned unused0 : 31; } b; unsigned long w; } IOMMU_PC_IVLD_ENABLE_REG

20) IOMMU_DM_AUT_CTRL_REG0 | 0x00B0

typedef union iommu_dm_aut_ctrl_reg0 { struct { unsigned dm0_m0_rd_aut_ctrl : 1; unsigned dm0_m0_wt_aut_ctrl : 1; unsigned dm0_m1_rd_aut_ctrl : 1; unsigned dm0_m1_wt_aut_ctrl : 1; unsigned dm0_m2_rd_aut_ctrl : 1; unsigned dm0_m2_wt_aut_ctrl : 1; unsigned dm0_m3_rd_aut_ctrl : 1; unsigned dm0_m3_wt_aut_ctrl : 1; unsigned dm0_m4_rd_aut_ctrl : 1; unsigned dm0_m4_wt_aut_ctrl : 1; unsigned dm0_m5_rd_aut_ctrl : 1; unsigned dm0_m5_wt_aut_ctrl : 1; unsigned dm0_m6_rd_aut_ctrl : 1; unsigned dm0_m6_wt_aut_ctrl : 1; unsigned unused0 : 2; unsigned dm1_m0_rd_aut_ctrl : 1; unsigned dm1_m0_wt_aut_ctrl : 1; unsigned dm1_m1_rd_aut_ctrl : 1; unsigned dm1_m1_wt_aut_ctrl : 1; unsigned dm1_m2_rd_aut_ctrl : 1; unsigned dm1_m2_wt_aut_ctrl : 1; unsigned dm1_m3_rd_aut_ctrl : 1; unsigned dm1_m3_wt_aut_ctrl : 1; unsigned dm1_m4_rd_aut_ctrl : 1; unsigned dm1_m4_wt_aut_ctrl : 1; unsigned dm1_m5_rd_aut_ctrl : 1; unsigned dm1_m5_wt_aut_ctrl : 1; unsigned dm1_m6_rd_aut_ctrl : 1; unsigned dm1_m6_wt_aut_ctrl : 1; unsigned unused1 : 2; } b; unsigned long w; } IOMMU_DM_AUT_CTRL_REG0

21) IOMMU_DM_AUT_CTRL_REG1 | 0x00B4

typedef union iommu_dm_aut_ctrl_reg1 { struct { unsigned dm2_m0_rd_aut_ctrl : 1; unsigned dm2_m0_wt_aut_ctrl : 1; unsigned dm2_m1_rd_aut_ctrl : 1; unsigned dm2_m1_wt_aut_ctrl : 1; unsigned dm2_m2_rd_aut_ctrl : 1; unsigned dm2_m2_wt_aut_ctrl : 1; unsigned dm2_m3_rd_aut_ctrl : 1; unsigned dm2_m3_wt_aut_ctrl : 1; unsigned dm2_m4_rd_aut_ctrl : 1; unsigned dm2_m4_wt_aut_ctrl : 1; unsigned dm2_m5_rd_aut_ctrl : 1; unsigned dm2_m5_wt_aut_ctrl : 1; unsigned dm2_m6_rd_aut_ctrl : 1; unsigned dm2_m6_wt_aut_ctrl : 1; unsigned unused0 : 2; unsigned dm3_m0_rd_aut_ctrl : 1; unsigned dm3_m0_wt_aut_ctrl : 1; unsigned dm3_m1_rd_aut_ctrl : 1; unsigned dm3_m1_wt_aut_ctrl : 1; unsigned dm3_m2_rd_aut_ctrl : 1; unsigned dm3_m2_wt_aut_ctrl : 1; unsigned dm3_m3_rd_aut_ctrl : 1; unsigned dm3_m3_wt_aut_ctrl : 1; unsigned dm3_m4_rd_aut_ctrl : 1; unsigned dm3_m4_wt_aut_ctrl : 1; unsigned dm3_m5_rd_aut_ctrl : 1; unsigned dm3_m5_wt_aut_ctrl : 1; unsigned dm3_m6_rd_aut_ctrl : 1; unsigned dm3_m6_wt_aut_ctrl : 1; unsigned unused1 : 2; } b; unsigned long w; } IOMMU_DM_AUT_CTRL_REG1

22) IOMMU_DM_AUT_CTRL_REG2 | 0x00B8

typedef union iommu_dm_aut_ctrl_reg2 { struct { unsigned dm4_m0_rd_aut_ctrl : 1; unsigned dm4_m0_wt_aut_ctrl : 1; unsigned dm4_m1_rd_aut_ctrl : 1; unsigned dm4_m1_wt_aut_ctrl : 1; unsigned dm4_m2_rd_aut_ctrl : 1; unsigned dm4_m2_wt_aut_ctrl : 1; unsigned dm4_m3_rd_aut_ctrl : 1; unsigned dm4_m3_wt_aut_ctrl : 1; unsigned dm4_m4_rd_aut_ctrl : 1; unsigned dm4_m4_wt_aut_ctrl : 1; unsigned dm4_m5_rd_aut_ctrl : 1; unsigned dm4_m5_wt_aut_ctrl : 1; unsigned dm4_m6_rd_aut_ctrl : 1; unsigned dm4_m6_wt_aut_ctrl : 1; unsigned unused0 : 2; unsigned dm5_m0_rd_aut_ctrl : 1; unsigned dm5_m0_wt_aut_ctrl : 1; unsigned dm5_m1_rd_aut_ctrl : 1; unsigned dm5_m1_wt_aut_ctrl : 1; unsigned dm5_m2_rd_aut_ctrl : 1; unsigned dm5_m2_wt_aut_ctrl : 1; unsigned dm5_m3_rd_aut_ctrl : 1; unsigned dm5_m3_wt_aut_ctrl : 1; unsigned dm5_m4_rd_aut_ctrl : 1; unsigned dm5_m4_wt_aut_ctrl : 1; unsigned dm5_m5_rd_aut_ctrl : 1; unsigned dm5_m5_wt_aut_ctrl : 1; unsigned dm5_m6_rd_aut_ctrl : 1; unsigned dm5_m6_wt_aut_ctrl : 1; unsigned unused1 : 2; } b; unsigned long w; } IOMMU_DM_AUT_CTRL_REG2

23) IOMMU_DM_AUT_CTRL_REG3 | 0x00BC

typedef union iommu_dm_aut_ctrl_reg3 { struct { unsigned dm6_m0_rd_aut_ctrl : 1; unsigned dm6_m0_wt_aut_ctrl : 1; unsigned dm6_m1_rd_aut_ctrl : 1; unsigned dm6_m1_wt_aut_ctrl : 1; unsigned dm6_m2_rd_aut_ctrl : 1; unsigned dm6_m2_wt_aut_ctrl : 1; unsigned dm6_m3_rd_aut_ctrl : 1; unsigned dm6_m3_wt_aut_ctrl : 1; unsigned dm6_m4_rd_aut_ctrl : 1; unsigned dm6_m4_wt_aut_ctrl : 1; unsigned dm6_m5_rd_aut_ctrl : 1; unsigned dm6_m5_wt_aut_ctrl : 1; unsigned dm6_m6_rd_aut_ctrl : 1; unsigned dm6_m6_wt_aut_ctrl : 1; unsigned unused0 : 2; unsigned dm7_m0_rd_aut_ctrl : 1; unsigned dm7_m0_wt_aut_ctrl : 1; unsigned dm7_m1_rd_aut_ctrl : 1; unsigned dm7_m1_wt_aut_ctrl : 1; unsigned dm7_m2_rd_aut_ctrl : 1; unsigned dm7_m2_wt_aut_ctrl : 1; unsigned dm7_m3_rd_aut_ctrl : 1; unsigned dm7_m3_wt_aut_ctrl : 1; unsigned dm7_m4_rd_aut_ctrl : 1; unsigned dm7_m4_wt_aut_ctrl : 1; unsigned dm7_m5_rd_aut_ctrl : 1; unsigned dm7_m5_wt_aut_ctrl : 1; unsigned dm7_m6_rd_aut_ctrl : 1; unsigned dm7_m6_wt_aut_ctrl : 1; unsigned unused1 : 2; } b; unsigned long w; } IOMMU_DM_AUT_CTRL_REG3

24) IOMMU_DM_AUT_CTRL_REG4 | 0x00C0

typedef union iommu_dm_aut_ctrl_reg4 { struct { unsigned dm8_m0_rd_aut_ctrl : 1; unsigned dm8_m0_wt_aut_ctrl : 1; unsigned dm8_m1_rd_aut_ctrl : 1; unsigned dm8_m1_wt_aut_ctrl : 1; unsigned dm8_m2_rd_aut_ctrl : 1; unsigned dm8_m2_wt_aut_ctrl : 1; unsigned dm8_m3_rd_aut_ctrl : 1; unsigned dm8_m3_wt_aut_ctrl : 1; unsigned dm8_m4_rd_aut_ctrl : 1; unsigned dm8_m4_wt_aut_ctrl : 1; unsigned dm8_m5_rd_aut_ctrl : 1; unsigned dm8_m5_wt_aut_ctrl : 1; unsigned dm8_m6_rd_aut_ctrl : 1; unsigned dm8_m6_wt_aut_ctrl : 1; unsigned unused0 : 2; unsigned dm9_m0_rd_aut_ctrl : 1; unsigned dm9_m0_wt_aut_ctrl : 1; unsigned dm9_m1_rd_aut_ctrl : 1; unsigned dm9_m1_wt_aut_ctrl : 1; unsigned dm9_m2_rd_aut_ctrl : 1; unsigned dm9_m2_wt_aut_ctrl : 1; unsigned dm9_m3_rd_aut_ctrl : 1; unsigned dm9_m3_wt_aut_ctrl : 1; unsigned dm9_m4_rd_aut_ctrl : 1; unsigned dm9_m4_wt_aut_ctrl : 1; unsigned dm9_m5_rd_aut_ctrl : 1; unsigned dm9_m5_wt_aut_ctrl : 1; unsigned dm9_m6_rd_aut_ctrl : 1; unsigned dm9_m6_wt_aut_ctrl : 1; unsigned unused1 : 2; } b; unsigned long w; } IOMMU_DM_AUT_CTRL_REG4

25) IOMMU_DM_AUT_CTRL_REG5 | 0x00C4

typedef union iommu_dm_aut_ctrl_reg5 { struct { unsigned dm10_m0_rd_aut_ctrl : 1; unsigned dm10_m0_wt_aut_ctrl : 1; unsigned dm10_m1_rd_aut_ctrl : 1; unsigned dm10_m1_wt_aut_ctrl : 1; unsigned dm10_m2_rd_aut_ctrl : 1; unsigned dm10_m2_wt_aut_ctrl : 1; unsigned dm10_m3_rd_aut_ctrl : 1; unsigned dm10_m3_wt_aut_ctrl : 1; unsigned dm10_m4_rd_aut_ctrl : 1; unsigned dm10_m4_wt_aut_ctrl : 1; unsigned dm10_m5_rd_aut_ctrl : 1; unsigned dm10_m5_wt_aut_ctrl : 1; unsigned dm10_m6_rd_aut_ctrl : 1; unsigned dm10_m6_wt_aut_ctrl : 1; unsigned unused0 : 2; unsigned dm11_m0_rd_aut_ctrl : 1; unsigned dm11_m0_wt_aut_ctrl : 1; unsigned dm11_m1_rd_aut_ctrl : 1; unsigned dm11_m1_wt_aut_ctrl : 1; unsigned dm11_m2_rd_aut_ctrl : 1; unsigned dm11_m2_wt_aut_ctrl : 1; unsigned dm11_m3_rd_aut_ctrl : 1; unsigned dm11_m3_wt_aut_ctrl : 1; unsigned dm11_m4_rd_aut_ctrl : 1; unsigned dm11_m4_wt_aut_ctrl : 1; unsigned dm11_m5_rd_aut_ctrl : 1; unsigned dm11_m5_wt_aut_ctrl : 1; unsigned dm11_m6_rd_aut_ctrl : 1; unsigned dm11_m6_wt_aut_ctrl : 1; unsigned unused1 : 2; } b; unsigned long w; } IOMMU_DM_AUT_CTRL_REG5

26) IOMMU_DM_AUT_CTRL_REG6 | 0x00C8

typedef union iommu_dm_aut_ctrl_reg6 { struct { unsigned dm12_m0_rd_aut_ctrl : 1; unsigned dm12_m0_wt_aut_ctrl : 1; unsigned dm12_m1_rd_aut_ctrl : 1; unsigned dm12_m1_wt_aut_ctrl : 1; unsigned dm12_m2_rd_aut_ctrl : 1; unsigned dm12_m2_wt_aut_ctrl : 1; unsigned dm12_m3_rd_aut_ctrl : 1; unsigned dm12_m3_wt_aut_ctrl : 1; unsigned dm12_m4_rd_aut_ctrl : 1; unsigned dm12_m4_wt_aut_ctrl : 1; unsigned dm12_m5_rd_aut_ctrl : 1; unsigned dm12_m5_wt_aut_ctrl : 1; unsigned dm12_m6_rd_aut_ctrl : 1; unsigned dm12_m6_wt_aut_ctrl : 1; unsigned unused0 : 2; unsigned dm13_m0_rd_aut_ctrl : 1; unsigned dm13_m0_wt_aut_ctrl : 1; unsigned dm13_m1_rd_aut_ctrl : 1; unsigned dm13_m1_wt_aut_ctrl : 1; unsigned dm13_m2_rd_aut_ctrl : 1; unsigned dm13_m2_wt_aut_ctrl : 1; unsigned dm13_m3_rd_aut_ctrl : 1; unsigned dm13_m3_wt_aut_ctrl : 1; unsigned dm13_m4_rd_aut_ctrl : 1; unsigned dm13_m4_wt_aut_ctrl : 1; unsigned dm13_m5_rd_aut_ctrl : 1; unsigned dm13_m5_wt_aut_ctrl : 1; unsigned dm13_m6_rd_aut_ctrl : 1; unsigned dm13_m6_wt_aut_ctrl : 1; unsigned unused1 : 2; } b; unsigned long w; } IOMMU_DM_AUT_CTRL_REG6

27) IOMMU_DM_AUT_CTRL_REG7 | 0x00CC

typedef union iommu_dm_aut_ctrl_reg7 { struct { unsigned dm14_m0_rd_aut_ctrl : 1; unsigned dm14_m0_wt_aut_ctrl : 1; unsigned dm14_m1_rd_aut_ctrl : 1; unsigned dm14_m1_wt_aut_ctrl : 1; unsigned dm14_m2_rd_aut_ctrl : 1; unsigned dm14_m2_wt_aut_ctrl : 1; unsigned dm14_m3_rd_aut_ctrl : 1; unsigned dm14_m3_wt_aut_ctrl : 1; unsigned dm14_m4_rd_aut_ctrl : 1; unsigned dm14_m4_wt_aut_ctrl : 1; unsigned dm14_m5_rd_aut_ctrl : 1; unsigned dm14_m5_wt_aut_ctrl : 1; unsigned dm14_m6_rd_aut_ctrl : 1; unsigned dm14_m6_wt_aut_ctrl : 1; unsigned unused0 : 2; unsigned dm15_m0_rd_aut_ctrl : 1; unsigned dm15_m0_wt_aut_ctrl : 1; unsigned dm15_m1_rd_aut_ctrl : 1; unsigned dm15_m1_wt_aut_ctrl : 1; unsigned dm15_m2_rd_aut_ctrl : 1; unsigned dm15_m2_wt_aut_ctrl : 1; unsigned dm15_m3_rd_aut_ctrl : 1; unsigned dm15_m3_wt_aut_ctrl : 1; unsigned dm15_m4_rd_aut_ctrl : 1; unsigned dm15_m4_wt_aut_ctrl : 1; unsigned dm15_m5_rd_aut_ctrl : 1; unsigned dm15_m5_wt_aut_ctrl : 1; unsigned dm15_m6_rd_aut_ctrl : 1; unsigned dm15_m6_wt_aut_ctrl : 1; unsigned unused1 : 2; } b; unsigned long w; } IOMMU_DM_AUT_CTRL_REG7

28) IOMMU_DM_AUT_OVWT_REG | 0x00D0

typedef union iommu_dm_aut_ovwt_reg { struct { unsigned m0_rd_aut_ovwt_ctrl : 1; unsigned m0_wt_aut_ovwt_ctrl : 1; unsigned m1_rd_aut_ovwt_ctrl : 1; unsigned m1_wt_aut_ovwt_ctrl : 1; unsigned m2_rd_aut_ovwt_ctrl : 1; unsigned m2_wt_aut_ovwt_ctrl : 1; unsigned m3_rd_aut_ovwt_ctrl : 1; unsigned m3_wt_aut_ovwt_ctrl : 1; unsigned m4_rd_aut_ovwt_ctrl : 1; unsigned m4_wt_aut_ovwt_ctrl : 1; unsigned m5_rd_aut_ovwt_ctrl : 1; unsigned m5_wt_aut_ovwt_ctrl : 1; unsigned m6_rd_aut_ovwt_ctrl : 1; unsigned m6_wt_aut_ovwt_ctrl : 1; unsigned unused0 : 17; unsigned dm_aut_ovwt_enable : 1; } b; unsigned long w; } IOMMU_DM_AUT_OVWT_REG

29) IOMMU_INT_ENABLE_REG | 0x0100

typedef union iommu_int_enable_reg { struct { unsigned micro_tlb0_invalid_en : 1; unsigned micro_tlb1_invalid_en : 1; unsigned micro_tlb2_invalid_en : 1; unsigned micro_tlb3_invalid_en : 1; unsigned micro_tlb4_invalid_en : 1; unsigned micro_tlb5_invalid_en : 1; unsigned micro_tlb6_invalid_en : 1; unsigned unused0 : 9; unsigned l1_page_table_invalid_en : 1; unsigned l2_page_table_invalid_en : 1; unsigned unused1 : 14; } b; unsigned long w; } IOMMU_INT_ENABLE_REG

30) IOMMU_INT_CLR_REG | 0x0104

typedef union iommu_int_clr_reg { struct { unsigned micro_tlb0_invalid_clr : 1; unsigned micro_tlb1_invalid_clr : 1; unsigned micro_tlb2_invalid_clr : 1; unsigned micro_tlb3_invalid_clr : 1; unsigned micro_tlb4_invalid_clr : 1; unsigned micro_tlb5_invalid_clr : 1; unsigned micro_tlb6_invalid_clr : 1; unsigned unused0 : 9; unsigned l1_page_table_invalid_clr : 1; unsigned l2_page_table_invalid_clr : 1; unsigned unused1 : 14; } b; unsigned long w; } IOMMU_INT_CLR_REG

31) IOMMU_INT_STA_REG | 0x0108

typedef union iommu_int_sta_reg { struct { unsigned micro_tlb0_invalid_sta : 1; unsigned micro_tlb1_invalid_sta : 1; unsigned micro_tlb2_invalid_sta : 1; unsigned micro_tlb3_invalid_sta : 1; unsigned micro_tlb4_invalid_sta : 1; unsigned micro_tlb5_invalid_sta : 1; unsigned micro_tlb6_invalid_sta : 1; unsigned unused0 : 9; unsigned l1_page_table_invalid_sta : 1; unsigned l2_page_table_invalid_sta : 1; unsigned unused1 : 14; } b; unsigned long w; } IOMMU_INT_STA_REG

32) IOMMU_INT_ERR_ADDR_REG0 | 0x0110

typedef union iommu_int_err_addr_reg0 { struct { unsigned int_err_addr0 : 32; } b; unsigned long w; } IOMMU_INT_ERR_ADDR_REG0

33) IOMMU_INT_ERR_ADDR_REG1 | 0x0114

typedef union iommu_int_err_addr_reg1 { struct { unsigned int_err_addr1 : 32; } b; unsigned long w; } IOMMU_INT_ERR_ADDR_REG1

34) IOMMU_INT_ERR_ADDR_REG2 | 0x0118

typedef union iommu_int_err_addr_reg2 { struct { unsigned int_err_addr2 : 32; } b; unsigned long w; } IOMMU_INT_ERR_ADDR_REG2

35) IOMMU_INT_ERR_ADDR_REG3 | 0x011C

typedef union iommu_int_err_addr_reg3 { struct { unsigned int_err_addr3 : 32; } b; unsigned long w; } IOMMU_INT_ERR_ADDR_REG3

36) IOMMU_INT_ERR_ADDR_REG4 | 0x0120

typedef union iommu_int_err_addr_reg4 { struct { unsigned int_err_addr4 : 32; } b; unsigned long w; } IOMMU_INT_ERR_ADDR_REG4

37) IOMMU_INT_ERR_ADDR_REG5 | 0x0124

typedef union iommu_int_err_addr_reg5 { struct { unsigned int_err_addr5 : 32; } b; unsigned long w; } IOMMU_INT_ERR_ADDR_REG5

38) IOMMU_INT_ERR_ADDR_REG6 | 0x0128

typedef union iommu_int_err_addr_reg6 { struct { unsigned int_err_addr6 : 32; } b; unsigned long w; } IOMMU_INT_ERR_ADDR_REG6

39) IOMMU_INT_ERR_ADDR_REG7 | 0x0130

typedef union iommu_int_err_addr_reg7 { struct { unsigned int_err_addr7 : 32; } b; unsigned long w; } IOMMU_INT_ERR_ADDR_REG7

40) IOMMU_INT_ERR_ADDR_REG8 | 0x0134

typedef union iommu_int_err_addr_reg8 { struct { unsigned int_err_addr8 : 32; } b; unsigned long w; } IOMMU_INT_ERR_ADDR_REG8

41) IOMMU_INT_ERR_DATA_REG0 | 0x0150

typedef union iommu_int_err_data_reg0 { struct { unsigned int_err_data0 : 32; } b; unsigned long w; } IOMMU_INT_ERR_DATA_REG0

42) IOMMU_INT_ERR_DATA_REG1 | 0x0154

typedef union iommu_int_err_data_reg1 { struct { unsigned int_err_data1 : 32; } b; unsigned long w; } IOMMU_INT_ERR_DATA_REG1

43) IOMMU_INT_ERR_DATA_REG2 | 0x0158

typedef union iommu_int_err_data_reg2 { struct { unsigned int_err_data2 : 32; } b; unsigned long w; } IOMMU_INT_ERR_DATA_REG2

44) IOMMU_INT_ERR_DATA_REG3 | 0x015C

typedef union iommu_int_err_data_reg3 { struct { unsigned int_err_data3 : 32; } b; unsigned long w; } IOMMU_INT_ERR_DATA_REG3

45) IOMMU_INT_ERR_DATA_REG4 | 0x0160

typedef union iommu_int_err_data_reg4 { struct { unsigned int_err_data4 : 32; } b; unsigned long w; } IOMMU_INT_ERR_DATA_REG4

46) IOMMU_INT_ERR_DATA_REG5 | 0x0164

typedef union iommu_int_err_data_reg5 { struct { unsigned int_err_data5 : 32; } b; unsigned long w; } IOMMU_INT_ERR_DATA_REG5

47) IOMMU_INT_ERR_DATA_REG6 | 0x0168

typedef union iommu_int_err_data_reg6 { struct { unsigned int_err_data6 : 32; } b; unsigned long w; } IOMMU_INT_ERR_DATA_REG6

48) IOMMU_INT_ERR_DATA_REG7 | 0x0170

typedef union iommu_int_err_data_reg7 { struct { unsigned int_err_data7 : 32; } b; unsigned long w; } IOMMU_INT_ERR_DATA_REG7

49) IOMMU_INT_ERR_DATA_REG8 | 0x0174

typedef union iommu_int_err_data_reg8 { struct { unsigned int_err_data8 : 32; } b; unsigned long w; } IOMMU_INT_ERR_DATA_REG8

50) IOMMU_L1PG_INT_REG | 0x0180

typedef union iommu_l1pg_int_reg { struct { unsigned master0_l1pg_int : 1; unsigned master1_l1pg_int : 1; unsigned master2_l1pg_int : 1; unsigned master3_l1pg_int : 1; unsigned master4_l1pg_int : 1; unsigned master5_l1pg_int : 1; unsigned master6_l1pg_int : 1; unsigned unused0 : 24; unsigned dbg_mode_l1pg_int : 1; } b; unsigned long w; } IOMMU_L1PG_INT_REG

51) IOMMU_L2PG_INT_REG | 0x0184

typedef union iommu_l2pg_int_reg { struct { unsigned master0_l2pg_int : 1; unsigned master1_l2pg_int : 1; unsigned master2_l2pg_int : 1; unsigned master3_l2pg_int : 1; unsigned master4_l2pg_int : 1; unsigned master5_l2pg_int : 1; unsigned master6_l2pg_int : 1; unsigned unused0 : 24; unsigned dbg_mode_l2pg_int : 1; } b; unsigned long w; } IOMMU_L2PG_INT_REG

52) IOMMU_VA_REG | 0x0190

typedef union iommu_va_reg { struct { unsigned virt_addr : 32; } b; unsigned long w; } IOMMU_VA_REG

53) IOMMU_VA_DATA_REG | 0x0194

typedef union iommu_va_data_reg { struct { unsigned va_data : 32; } b; unsigned long w; } IOMMU_VA_DATA_REG

54) IOMMU_VA_CONFIG_REG | 0x0198

typedef union iommu_va_config_reg { struct { unsigned va_config_start : 1; unsigned unused0 : 7; unsigned va_config : 1; unsigned unused1 : 22; unsigned mode_sel : 1; } b; unsigned long w; } IOMMU_VA_CONFIG_REG

55) IOMMU_PMU_ENABLE_REG | 0x0200

typedef union iommu_pmu_enable_reg { struct { unsigned pmu_enable : 1; unsigned unused0 : 31; } b; unsigned long w; } IOMMU_PMU_ENABLE_REG

56) IOMMU_PMU_CLR_REG | 0x0210

typedef union iommu_pmu_clr_reg { struct { unsigned pmu_clr : 1; unsigned unused0 : 31; } b; unsigned long w; } IOMMU_PMU_CLR_REG

57) IOMMU_PMU_ACCESS_LOW_REG0 | 0x0230

typedef union iommu_pmu_access_low_reg0 { struct { unsigned pmu_access_low0 : 32; } b; unsigned long w; } IOMMU_PMU_ACCESS_LOW_REG0

58) IOMMU_PMU_ACCESS_HIGH_REG0 | 0x0234

typedef union iommu_pmu_access_high_reg0 { struct { unsigned pmu_access_high0 : 11; unsigned unused0 : 21; } b; unsigned long w; } IOMMU_PMU_ACCESS_HIGH_REG0

59) IOMMU_PMU_HIT_LOW_REG0 | 0x0238

typedef union iommu_pmu_hit_low_reg0 { struct { unsigned pmu_hit_low0 : 32; } b; unsigned long w; } IOMMU_PMU_HIT_LOW_REG0

60) IOMMU_PMU_HIT_HIGH_REG0 | 0x023C

typedef union iommu_pmu_hit_high_reg0 { struct { unsigned pmu_hit_high0 : 11; unsigned unused0 : 21; } b; unsigned long w; } IOMMU_PMU_HIT_HIGH_REG0

61) IOMMU_PMU_ACCESS_LOW_REG1 | 0x0240

typedef union iommu_pmu_access_low_reg1 { struct { unsigned pmu_access_low1 : 32; } b; unsigned long w; } IOMMU_PMU_ACCESS_LOW_REG1

62) IOMMU_PMU_ACCESS_HIGH_REG1 | 0x0244

typedef union iommu_pmu_access_high_reg1 { struct { unsigned pmu_access_high1 : 11; unsigned unused0 : 21; } b; unsigned long w; } IOMMU_PMU_ACCESS_HIGH_REG1

63) IOMMU_PMU_HIT_LOW_REG1 | 0x0248

typedef union iommu_pmu_hit_low_reg1 { struct { unsigned pmu_hit_low1 : 32; } b; unsigned long w; } IOMMU_PMU_HIT_LOW_REG1

64) IOMMU_PMU_HIT_HIGH_REG1 | 0x024C

typedef union iommu_pmu_hit_high_reg1 { struct { unsigned pmu_hit_high1 : 11; unsigned unused0 : 21; } b; unsigned long w; } IOMMU_PMU_HIT_HIGH_REG1

65) IOMMU_PMU_ACCESS_LOW_REG2 | 0x0250

typedef union iommu_pmu_access_low_reg2 { struct { unsigned pmu_access_low2 : 32; } b; unsigned long w; } IOMMU_PMU_ACCESS_LOW_REG2

66) IOMMU_PMU_ACCESS_HIGH_REG2 | 0x0254

typedef union iommu_pmu_access_high_reg2 { struct { unsigned pmu_access_high2 : 11; unsigned unused0 : 21; } b; unsigned long w; } IOMMU_PMU_ACCESS_HIGH_REG2

67) IOMMU_PMU_HIT_LOW_REG2 | 0x0258

typedef union iommu_pmu_hit_low_reg2 { struct { unsigned pmu_hit_low2 : 32; } b; unsigned long w; } IOMMU_PMU_HIT_LOW_REG2

68) IOMMU_PMU_HIT_HIGH_REG2 | 0x025C

typedef union iommu_pmu_hit_high_reg2 { struct { unsigned pmu_hit_high2 : 11; unsigned unused0 : 21; } b; unsigned long w; } IOMMU_PMU_HIT_HIGH_REG2

69) IOMMU_PMU_ACCESS_LOW_REG3 | 0x0260

typedef union iommu_pmu_access_low_reg3 { struct { unsigned pmu_access_low3 : 32; } b; unsigned long w; } IOMMU_PMU_ACCESS_LOW_REG3

70) IOMMU_PMU_ACCESS_HIGH_REG3 | 0x0264

typedef union iommu_pmu_access_high_reg3 { struct { unsigned pmu_access_high3 : 11; unsigned unused0 : 21; } b; unsigned long w; } IOMMU_PMU_ACCESS_HIGH_REG3

71) IOMMU_PMU_HIT_LOW_REG3 | 0x0268

typedef union iommu_pmu_hit_low_reg3 { struct { unsigned pmu_hit_low3 : 32; } b; unsigned long w; } IOMMU_PMU_HIT_LOW_REG3

72) IOMMU_PMU_HIT_HIGH_REG3 | 0x026C

typedef union iommu_pmu_hit_high_reg3 { struct { unsigned pmu_hit_high3 : 11; unsigned unused0 : 21; } b; unsigned long w; } IOMMU_PMU_HIT_HIGH_REG3

73) IOMMU_PMU_ACCESS_LOW_REG4 | 0x0270

typedef union iommu_pmu_access_low_reg4 { struct { unsigned pmu_access_low4 : 32; } b; unsigned long w; } IOMMU_PMU_ACCESS_LOW_REG4

74) IOMMU_PMU_ACCESS_HIGH_REG4 | 0x0274

typedef union iommu_pmu_access_high_reg4 { struct { unsigned pmu_access_high4 : 11; unsigned unused0 : 21; } b; unsigned long w; } IOMMU_PMU_ACCESS_HIGH_REG4

75) IOMMU_PMU_HIT_LOW_REG4 | 0x0278

typedef union iommu_pmu_hit_low_reg4 { struct { unsigned pmu_hit_low4 : 32; } b; unsigned long w; } IOMMU_PMU_HIT_LOW_REG4

76) IOMMU_PMU_HIT_HIGH_REG4 | 0x027C

typedef union iommu_pmu_hit_high_reg4 { struct { unsigned pmu_hit_high4 : 11; unsigned unused0 : 21; } b; unsigned long w; } IOMMU_PMU_HIT_HIGH_REG4

77) IOMMU_PMU_ACCESS_LOW_REG5 | 0x0280

typedef union iommu_pmu_access_low_reg5 { struct { unsigned pmu_access_low5 : 32; } b; unsigned long w; } IOMMU_PMU_ACCESS_LOW_REG5

78) IOMMU_PMU_ACCESS_HIGH_REG5 | 0x0284

typedef union iommu_pmu_access_high_reg5 { struct { unsigned pmu_access_high5 : 11; unsigned unused0 : 21; } b; unsigned long w; } IOMMU_PMU_ACCESS_HIGH_REG5

79) IOMMU_PMU_HIT_LOW_REG5 | 0x0288

typedef union iommu_pmu_hit_low_reg5 { struct { unsigned pmu_hit_low5 : 32; } b; unsigned long w; } IOMMU_PMU_HIT_LOW_REG5

80) IOMMU_PMU_HIT_HIGH_REG5 | 0x028C

typedef union iommu_pmu_hit_high_reg5 { struct { unsigned pmu_hit_high5 : 11; unsigned unused0 : 21; } b; unsigned long w; } IOMMU_PMU_HIT_HIGH_REG5

81) IOMMU_PMU_ACCESS_LOW_REG6 | 0x0290

typedef union iommu_pmu_access_low_reg6 { struct { unsigned pmu_access_low6 : 32; } b; unsigned long w; } IOMMU_PMU_ACCESS_LOW_REG6

82) IOMMU_PMU_ACCESS_HIGH_REG6 | 0x0294

typedef union iommu_pmu_access_high_reg6 { struct { unsigned pmu_access_high6 : 11; unsigned unused0 : 21; } b; unsigned long w; } IOMMU_PMU_ACCESS_HIGH_REG6

83) IOMMU_PMU_HIT_LOW_REG6 | 0x0298

typedef union iommu_pmu_hit_low_reg6 { struct { unsigned pmu_hit_low6 : 32; } b; unsigned long w; } IOMMU_PMU_HIT_LOW_REG6

84) IOMMU_PMU_HIT_HIGH_REG6 | 0x029C

typedef union iommu_pmu_hit_high_reg6 { struct { unsigned pmu_hit_high6 : 11; unsigned unused0 : 21; } b; unsigned long w; } IOMMU_PMU_HIT_HIGH_REG6

85) IOMMU_PMU_ACCESS_LOW_REG7 | 0x02D0

typedef union iommu_pmu_access_low_reg7 { struct { unsigned pmu_access_low7 : 32; } b; unsigned long w; } IOMMU_PMU_ACCESS_LOW_REG7

86) IOMMU_PMU_ACCESS_HIGH_REG7 | 0x02D4

typedef union iommu_pmu_access_high_reg7 { struct { unsigned pmu_access_high7 : 11; unsigned unused0 : 21; } b; unsigned long w; } IOMMU_PMU_ACCESS_HIGH_REG7

87) IOMMU_PMU_HIT_LOW_REG7 | 0x02D8

typedef union iommu_pmu_hit_low_reg7 { struct { unsigned pmu_hit_low7 : 32; } b; unsigned long w; } IOMMU_PMU_HIT_LOW_REG7

88) IOMMU_PMU_HIT_HIGH_REG7 | 0x02DC

typedef union iommu_pmu_hit_high_reg7 { struct { unsigned pmu_hit_high7 : 11; unsigned unused0 : 21; } b; unsigned long w; } IOMMU_PMU_HIT_HIGH_REG7

89) IOMMU_PMU_ACCESS_LOW_REG8 | 0x02E0

typedef union iommu_pmu_access_low_reg8 { struct { unsigned pmu_access_low8 : 32; } b; unsigned long w; } IOMMU_PMU_ACCESS_LOW_REG8

90) IOMMU_PMU_ACCESS_HIGH_REG8 | 0x02E4

typedef union iommu_pmu_access_high_reg8 { struct { unsigned pmu_access_high8 : 11; unsigned unused0 : 21; } b; unsigned long w; } IOMMU_PMU_ACCESS_HIGH_REG8

91) IOMMU_PMU_HIT_LOW_REG8 | 0x02E8

typedef union iommu_pmu_hit_low_reg8 { struct { unsigned pmu_hit_low8 : 32; } b; unsigned long w; } IOMMU_PMU_HIT_LOW_REG8

92) IOMMU_PMU_HIT_HIGH_REG8 | 0x02EC

typedef union iommu_pmu_hit_high_reg8 { struct { unsigned pmu_hit_high8 : 11; unsigned unused0 : 21; } b; unsigned long w; } IOMMU_PMU_HIT_HIGH_REG8

93) IOMMU_PMU_TL_LOW_REG0 | 0x0300

typedef union iommu_pmu_tl_low_reg0 { struct { unsigned pmu_tl_low0 : 32; } b; unsigned long w; } IOMMU_PMU_TL_LOW_REG0

94) IOMMU_PMU_TL_HIGH_REG0 | 0x0304

typedef union iommu_pmu_tl_high_reg0 { struct { unsigned pmu_tl_high0 : 18; unsigned unused0 : 14; } b; unsigned long w; } IOMMU_PMU_TL_HIGH_REG0

95) IOMMU_PMU_ML_REG0 | 0x0308

typedef union iommu_pmu_ml_reg0 { struct { unsigned pmu_ml0 : 32; } b; unsigned long w; } IOMMU_PMU_ML_REG0

96) IOMMU_PMU_TL_LOW_REG1 | 0x0310

typedef union iommu_pmu_tl_low_reg1 { struct { unsigned pmu_tl_low1 : 32; } b; unsigned long w; } IOMMU_PMU_TL_LOW_REG1

97) IOMMU_PMU_TL_HIGH_REG1 | 0x0314

typedef union iommu_pmu_tl_high_reg1 { struct { unsigned pmu_tl_high1 : 18; unsigned unused0 : 14; } b; unsigned long w; } IOMMU_PMU_TL_HIGH_REG1

98) IOMMU_PMU_ML_REG1 | 0x0318

typedef union iommu_pmu_ml_reg1 { struct { unsigned pmu_ml1 : 32; } b; unsigned long w; } IOMMU_PMU_ML_REG1

99) IOMMU_PMU_TL_LOW_REG2 | 0x0320

typedef union iommu_pmu_tl_low_reg2 { struct { unsigned pmu_tl_low2 : 32; } b; unsigned long w; } IOMMU_PMU_TL_LOW_REG2

100) IOMMU_PMU_TL_HIGH_REG2 | 0x0324

typedef union iommu_pmu_tl_high_reg2 { struct { unsigned pmu_tl_high2 : 18; unsigned unused0 : 14; } b; unsigned long w; } IOMMU_PMU_TL_HIGH_REG2

101) IOMMU_PMU_ML_REG2 | 0x0328

typedef union iommu_pmu_ml_reg2 { struct { unsigned pmu_ml2 : 32; } b; unsigned long w; } IOMMU_PMU_ML_REG2

102) IOMMU_PMU_TL_LOW_REG3 | 0x0330

typedef union iommu_pmu_tl_low_reg3 { struct { unsigned pmu_tl_low3 : 32; } b; unsigned long w; } IOMMU_PMU_TL_LOW_REG3

103) IOMMU_PMU_TL_HIGH_REG3 | 0x0334

typedef union iommu_pmu_tl_high_reg3 { struct { unsigned pmu_tl_high3 : 18; unsigned unused0 : 14; } b; unsigned long w; } IOMMU_PMU_TL_HIGH_REG3

104) IOMMU_PMU_ML_REG3 | 0x0338

typedef union iommu_pmu_ml_reg3 { struct { unsigned pmu_ml3 : 32; } b; unsigned long w; } IOMMU_PMU_ML_REG3

105) IOMMU_PMU_TL_LOW_REG4 | 0x0340

typedef union iommu_pmu_tl_low_reg4 { struct { unsigned pmu_tl_low4 : 32; } b; unsigned long w; } IOMMU_PMU_TL_LOW_REG4

106) IOMMU_PMU_TL_HIGH_REG4 | 0x0344

typedef union iommu_pmu_tl_high_reg4 { struct { unsigned pmu_tl_high4 : 18; unsigned unused0 : 14; } b; unsigned long w; } IOMMU_PMU_TL_HIGH_REG4

107) IOMMU_PMU_ML_REG4 | 0x0348

typedef union iommu_pmu_ml_reg4 { struct { unsigned pmu_ml4 : 32; } b; unsigned long w; } IOMMU_PMU_ML_REG4

108) IOMMU_PMU_TL_LOW_REG5 | 0x0350

typedef union iommu_pmu_tl_low_reg5 { struct { unsigned pmu_tl_low5 : 32; } b; unsigned long w; } IOMMU_PMU_TL_LOW_REG5

109) IOMMU_PMU_TL_HIGH_REG5 | 0x0354

typedef union iommu_pmu_tl_high_reg5 { struct { unsigned pmu_tl_high5 : 18; unsigned unused0 : 14; } b; unsigned long w; } IOMMU_PMU_TL_HIGH_REG5

110) IOMMU_PMU_ML_REG5 | 0x0358

typedef union iommu_pmu_ml_reg5 { struct { unsigned pmu_ml5 : 32; } b; unsigned long w; } IOMMU_PMU_ML_REG5

111) IOMMU_PMU_TL_LOW_REG6 | 0x0360

typedef union iommu_pmu_tl_low_reg6 { struct { unsigned pmu_tl_low6 : 32; } b; unsigned long w; } IOMMU_PMU_TL_LOW_REG6

112) IOMMU_PMU_TL_HIGH_REG6 | 0x0364

typedef union iommu_pmu_tl_high_reg6 { struct { unsigned pmu_tl_high6 : 18; unsigned unused0 : 14; } b; unsigned long w; } IOMMU_PMU_TL_HIGH_REG6

113) IOMMU_PMU_ML_REG6 | 0x0368

typedef union iommu_pmu_ml_reg6 { struct { unsigned pmu_ml6 : 32; } b; unsigned long w; } IOMMU_PMU_ML_REG6