Регистры H616: Контроллер синхрогенератора

Регистров: 124

Имя регистра | Смещение

typedef union pll_cpux_ctrl_reg { struct { unsigned pll_factor_m : 2; unsigned unused0 : 6; unsigned pll_factor_n : 8; unsigned pll_out_ext_divp : 2; unsigned unused1 : 6; unsigned pll_lock_time : 3; unsigned pll_output_enable : 1; unsigned lock : 1; unsigned lock_enable : 1; unsigned unused2 : 1; unsigned pll_enable : 1; } b; unsigned long w; } PLL_CPUX_CTRL_REG

2) PLL_DDR0_CTRL_REG | 0x0010

typedef union pll_ddr0_ctrl_reg { struct { unsigned pll_output_div_m0. : 1; unsigned pll_input_div_m1. : 1; unsigned unused0 : 6; unsigned pll_factor_n : 8; unsigned unused1 : 8; unsigned pll_sdm_enable : 1; unsigned unused2 : 2; unsigned pll_output_enable : 1; unsigned lock : 1; unsigned lock_enable : 1; unsigned unused3 : 1; unsigned pll_enable : 1; } b; unsigned long w; } PLL_DDR0_CTRL_REG

3) PLL_DDR1_CTRL_REG | 0x0018

typedef union pll_ddr1_ctrl_reg { struct { unsigned pll_output_div_m0. : 1; unsigned pll_input_div_m1. : 1; unsigned unused0 : 6; unsigned pll_factor_n : 8; unsigned unused1 : 8; unsigned pll_sdm_enable : 1; unsigned unused2 : 2; unsigned pll_output_enable : 1; unsigned lock : 1; unsigned lock_enable : 1; unsigned unused3 : 1; unsigned pll_enable : 1; } b; unsigned long w; } PLL_DDR1_CTRL_REG

4) PLL_PERI0_CTRL_REG | 0x0020

typedef union pll_peri0_ctrl_reg { struct { unsigned pll_output_div_m0 : 1; unsigned pll_input_div_m1 : 1; unsigned unused0 : 6; unsigned pll_factor_n : 8; unsigned unused1 : 8; unsigned pll_sdm_enable : 1; unsigned unused2 : 2; unsigned pll_output_enable : 1; unsigned lock : 1; unsigned lock_enable : 1; unsigned unused3 : 1; unsigned pll_enable : 1; } b; unsigned long w; } PLL_PERI0_CTRL_REG

5) PLL_PERI1_CTRL_REG | 0x0028

typedef union pll_peri1_ctrl_reg { struct { unsigned pll_output_div_m0 : 1; unsigned pll_input_div_m1 : 1; unsigned unused0 : 6; unsigned pll_factor_n : 8; unsigned unused1 : 8; unsigned pll_sdm_enable : 1; unsigned unused2 : 2; unsigned pll_output_enable : 1; unsigned lock : 1; unsigned lock_enable : 1; unsigned unused3 : 1; unsigned pll_enable : 1; } b; unsigned long w; } PLL_PERI1_CTRL_REG

6) PLL_GPU0_CTRL_REG | 0x0030

typedef union pll_gpu0_ctrl_reg { struct { unsigned pll_output_div_m0. : 1; unsigned pll_input_div_m1. : 1; unsigned unused0 : 6; unsigned pll_factor_n : 8; unsigned unused1 : 8; unsigned pll_sdm_enable : 1; unsigned unused2 : 2; unsigned pll_output_enable : 1; unsigned lock : 1; unsigned lock_enable : 1; unsigned unused3 : 1; unsigned pll_enable : 1; } b; unsigned long w; } PLL_GPU0_CTRL_REG

7) PLL_VIDEO0_CTRL_REG | 0x0040

typedef union pll_video0_ctrl_reg { struct { unsigned pll_output_div_d : 1; unsigned pll_input_div_m : 1; unsigned unused0 : 6; unsigned pll_factor_n : 8; unsigned unused1 : 8; unsigned pll_sdm_enable : 1; unsigned unused2 : 2; unsigned pll_output_enable : 1; unsigned lock : 1; unsigned lock_enable : 1; unsigned unused3 : 1; unsigned pll_enable : 1; } b; unsigned long w; } PLL_VIDEO0_CTRL_REG

8) PLL_VIDEO1_CTRL_REG | 0x0048

typedef union pll_video1_ctrl_reg { struct { unsigned pll_output_div_d : 1; unsigned pll_input_div_m : 1; unsigned unused0 : 6; unsigned pll_factor_n : 8; unsigned unused1 : 8; unsigned pll_sdm_enable : 1; unsigned unused2 : 2; unsigned pll_output_enable : 1; unsigned lock : 1; unsigned lock_enable : 1; unsigned unused3 : 1; unsigned pll_enable : 1; } b; unsigned long w; } PLL_VIDEO1_CTRL_REG

9) PLL_VE_CTRL_REG | 0x0058

typedef union pll_ve_ctrl_reg { struct { unsigned pll_output_div_m0. : 1; unsigned pll_input_div_m1. : 1; unsigned unused0 : 6; unsigned pll_factor_n : 8; unsigned unused1 : 8; unsigned pll_sdm_enable : 1; unsigned unused2 : 2; unsigned pll_output_enable : 1; unsigned lock : 1; unsigned lock_enable : 1; unsigned unused3 : 1; unsigned pll_enable : 1; } b; unsigned long w; } PLL_VE_CTRL_REG

10) PLL_DE_CTRL_REG | 0x0060

typedef union pll_de_ctrl_reg { struct { unsigned pll_output_div_m0. : 1; unsigned pll_input_div_m1. : 1; unsigned unused0 : 6; unsigned pll_factor_n : 8; unsigned unused1 : 8; unsigned pll_sdm_enable : 1; unsigned unused2 : 2; unsigned pll_output_enable : 1; unsigned lock : 1; unsigned lock_enable : 1; unsigned unused3 : 1; unsigned pll_enable : 1; } b; unsigned long w; } PLL_DE_CTRL_REG

11) PLL_AUDIO_CTRL_REG | 0x0078

typedef union pll_audio_ctrl_reg { struct { unsigned pll_output_div_m0 : 1; unsigned pll_input_div_m1 : 1; unsigned unused0 : 6; unsigned pll_factor_n : 8; unsigned pll_post_div_p : 6; unsigned unused1 : 2; unsigned pll_sdm_enable : 1; unsigned unused2 : 2; unsigned pll_output_enable : 1; unsigned lock : 1; unsigned lock_enable : 1; unsigned unused3 : 1; unsigned pll_enable : 1; } b; unsigned long w; } PLL_AUDIO_CTRL_REG

12) PLL_DDR0_PAT_CTRL_REG | 0x0110

typedef union pll_ddr0_pat_ctrl_reg { struct { unsigned wave_bot : 17; unsigned freq : 2; unsigned sdm_clk_sel : 1; unsigned wave_step : 9; unsigned spr_freq_mode : 2; unsigned sig_delt_pat_en : 1; } b; unsigned long w; } PLL_DDR0_PAT_CTRL_REG

13) PLL_DDR1_PAT_CTRL_REG | 0x0118

typedef union pll_ddr1_pat_ctrl_reg { struct { unsigned wave_bot : 17; unsigned freq : 2; unsigned sdm_clk_sel : 1; unsigned wave_step : 9; unsigned spr_freq_mode : 2; unsigned sig_delt_pat_en : 1; } b; unsigned long w; } PLL_DDR1_PAT_CTRL_REG

14) PLL_PERI0_PAT0_CTRL_REG | 0x0120

typedef union pll_peri0_pat0_ctrl_reg { struct { unsigned wave_bot : 17; unsigned freq : 2; unsigned sdm_clk_sel : 1; unsigned wave_step : 9; unsigned spr_freq_mode : 2; unsigned sig_delt_pat_en : 1; } b; unsigned long w; } PLL_PERI0_PAT0_CTRL_REG

15) PLL_PERI0_PAT1_CTRL_REG | 0x0124

typedef union pll_peri0_pat1_ctrl_reg { struct { unsigned frac_in : 17; unsigned unused0 : 3; unsigned frac_en : 1; unsigned unused1 : 3; unsigned dither_en : 1; unsigned unused2 : 7; } b; unsigned long w; } PLL_PERI0_PAT1_CTRL_REG

16) PLL_PERI1_PAT0_CTRL_REG | 0x0128

typedef union pll_peri1_pat0_ctrl_reg { struct { unsigned wave_bot : 17; unsigned freq : 2; unsigned sdm_clk_sel : 1; unsigned wave_step : 9; unsigned spr_freq_mode : 2; unsigned sig_delt_pat_en : 1; } b; unsigned long w; } PLL_PERI1_PAT0_CTRL_REG

17) PLL_PERI1_PAT1_CTRL_REG | 0x012C

typedef union pll_peri1_pat1_ctrl_reg { struct { unsigned frac_in : 17; unsigned unused0 : 3; unsigned frac_en : 1; unsigned unused1 : 3; unsigned dither_en : 1; unsigned unused2 : 7; } b; unsigned long w; } PLL_PERI1_PAT1_CTRL_REG

18) PLL_GPU0_PAT0_CTRL_REG | 0x0130

typedef union pll_gpu0_pat0_ctrl_reg { struct { unsigned wave_bot : 17; unsigned freq : 2; unsigned sdm_clk_sel : 1; unsigned wave_step : 9; unsigned spr_freq_mode : 2; unsigned sig_delt_pat_en : 1; } b; unsigned long w; } PLL_GPU0_PAT0_CTRL_REG

19) PLL_GPU0_PAT1_CTRL_REG | 0x0134

typedef union pll_gpu0_pat1_ctrl_reg { struct { unsigned frac_in : 17; unsigned unused0 : 3; unsigned frac_en : 1; unsigned unused1 : 3; unsigned dither_en : 1; unsigned unused2 : 7; } b; unsigned long w; } PLL_GPU0_PAT1_CTRL_REG

20) PLL_VIDEO0_PAT0_CTRL_REG | 0x0140

typedef union pll_video0_pat0_ctrl_reg { struct { unsigned wave_bot : 17; unsigned freq : 2; unsigned sdm_clk_sel : 1; unsigned wave_step : 9; unsigned spr_freq_mode : 2; unsigned sig_delt_pat_en : 1; } b; unsigned long w; } PLL_VIDEO0_PAT0_CTRL_REG

21) PLL_VIDEO0_PAT1_CTRL_REG | 0x0144

typedef union pll_video0_pat1_ctrl_reg { struct { unsigned frac_in : 17; unsigned unused0 : 3; unsigned frac_en : 1; unsigned unused1 : 3; unsigned dither_en : 1; unsigned unused2 : 7; } b; unsigned long w; } PLL_VIDEO0_PAT1_CTRL_REG

22) PLL_VIDEO1_PAT0_CTRL_REG | 0x0148

typedef union pll_video1_pat0_ctrl_reg { struct { unsigned wave_bot : 17; unsigned freq : 2; unsigned sdm_clk_sel : 1; unsigned wave_step : 9; unsigned spr_freq_mode : 2; unsigned sig_delt_pat_en : 1; } b; unsigned long w; } PLL_VIDEO1_PAT0_CTRL_REG

23) PLL_VIDEO1_PAT1_CTRL_REG | 0x014C

typedef union pll_video1_pat1_ctrl_reg { struct { unsigned frac_in : 17; unsigned unused0 : 3; unsigned frac_en : 1; unsigned unused1 : 3; unsigned dither_en : 1; unsigned unused2 : 7; } b; unsigned long w; } PLL_VIDEO1_PAT1_CTRL_REG

24) PLL_VE_PAT0_CTRL_REG | 0x0158

typedef union pll_ve_pat0_ctrl_reg { struct { unsigned wave_bot : 17; unsigned freq : 2; unsigned sdm_clk_sel : 1; unsigned wave_step : 9; unsigned spr_freq_mode : 2; unsigned sig_delt_pat_en : 1; } b; unsigned long w; } PLL_VE_PAT0_CTRL_REG

25) PLL_VE_PAT1_CTRL_REG | 0x015C

typedef union pll_ve_pat1_ctrl_reg { struct { unsigned frac_in : 17; unsigned unused0 : 3; unsigned frac_en : 1; unsigned unused1 : 3; unsigned dither_en : 1; unsigned unused2 : 7; } b; unsigned long w; } PLL_VE_PAT1_CTRL_REG

26) PLL_DE_PAT0_CTRL_REG | 0x0160

typedef union pll_de_pat0_ctrl_reg { struct { unsigned wave_bot : 17; unsigned freq : 2; unsigned sdm_clk_sel : 1; unsigned wave_step : 9; unsigned spr_freq_mode : 2; unsigned sig_delt_pat_en : 1; } b; unsigned long w; } PLL_DE_PAT0_CTRL_REG

27) PLL_DE_PAT1_CTRL_REG | 0x0164

typedef union pll_de_pat1_ctrl_reg { struct { unsigned frac_in : 17; unsigned unused0 : 3; unsigned frac_en : 1; unsigned unused1 : 3; unsigned dither_en : 1; unsigned unused2 : 7; } b; unsigned long w; } PLL_DE_PAT1_CTRL_REG

28) PLL_AUDIO_PAT0_CTRL_REG | 0x0178

typedef union pll_audio_pat0_ctrl_reg { struct { unsigned wave_bot : 17; unsigned freq : 2; unsigned sdm_clk_sel : 1; unsigned wave_step : 9; unsigned spr_freq_mode : 2; unsigned sig_delt_pat_en : 1; } b; unsigned long w; } PLL_AUDIO_PAT0_CTRL_REG

29) PLL_AUDIO_PAT1_CTRL_REG | 0x017C

typedef union pll_audio_pat1_ctrl_reg { struct { unsigned frac_in : 17; unsigned unused0 : 3; unsigned frac_en : 1; unsigned unused1 : 3; unsigned dither_en : 1; unsigned unused2 : 7; } b; unsigned long w; } PLL_AUDIO_PAT1_CTRL_REG

30) PLL_CPUX_BIAS_REG | 0x0300

typedef union pll_cpux_bias_reg { struct { unsigned unused0 : 16; unsigned pll_bias_current : 5; unsigned unused1 : 10; unsigned vco_rst : 1; } b; unsigned long w; } PLL_CPUX_BIAS_REG

31) PLL_DDR0_BIAS_REG | 0x0310

typedef union pll_ddr0_bias_reg { struct { unsigned unused0 : 16; unsigned pll_bias_ctrl. : 5; unsigned unused1 : 11; } b; unsigned long w; } PLL_DDR0_BIAS_REG

32) PLL_DDR1_BIAS_REG | 0x0318

typedef union pll_ddr1_bias_reg { struct { unsigned unused0 : 32; } b; unsigned long w; } PLL_DDR1_BIAS_REG

33) PLL_PERI0_BIAS_REG | 0x0320

typedef union pll_peri0_bias_reg { struct { unsigned unused0 : 16; unsigned pll_bias_ctrl : 5; unsigned unused1 : 11; } b; unsigned long w; } PLL_PERI0_BIAS_REG

34) PLL_PERI1_BIAS_REG | 0x0328

typedef union pll_peri1_bias_reg { struct { unsigned unused0 : 16; unsigned pll_bias_ctrl : 5; unsigned unused1 : 11; } b; unsigned long w; } PLL_PERI1_BIAS_REG

35) PLL_GPU0_BIAS_REG | 0x0330

typedef union pll_gpu0_bias_reg { struct { unsigned unused0 : 16; unsigned pll_bias_ctrl : 5; unsigned unused1 : 11; } b; unsigned long w; } PLL_GPU0_BIAS_REG

36) PLL_VIDEO0_BIAS_REG | 0x0340

typedef union pll_video0_bias_reg { struct { unsigned unused0 : 16; unsigned pll_bias_ctrl : 5; unsigned unused1 : 11; } b; unsigned long w; } PLL_VIDEO0_BIAS_REG

37) PLL_VIDEO1_BIAS_REG | 0x0348

typedef union pll_video1_bias_reg { struct { unsigned unused0 : 16; unsigned pll_bias_ctrl : 5; unsigned unused1 : 11; } b; unsigned long w; } PLL_VIDEO1_BIAS_REG

38) PLL_VE_BIAS_REG | 0x0358

typedef union pll_ve_bias_reg { struct { unsigned unused0 : 16; unsigned pll_bias_ctrl : 5; unsigned unused1 : 11; } b; unsigned long w; } PLL_VE_BIAS_REG

39) PLL_DE_BIAS_REG | 0x0360

typedef union pll_de_bias_reg { struct { unsigned unused0 : 16; unsigned pll_bias_ctrl : 5; unsigned unused1 : 11; } b; unsigned long w; } PLL_DE_BIAS_REG

40) PLL_AUDIO_BIAS_REG | 0x0378

typedef union pll_audio_bias_reg { struct { unsigned unused0 : 16; unsigned pll_bias_ctrl : 5; unsigned unused1 : 11; } b; unsigned long w; } PLL_AUDIO_BIAS_REG

41) PLL_CPUX_TUN_REG | 0x0400

typedef union pll_cpux_tun_reg { struct { unsigned c_b_out : 7; unsigned c_od1 : 1; unsigned c_b_in : 7; unsigned c_od0 : 1; unsigned cnt_init_ctrl : 7; unsigned unused0 : 1; unsigned kvco_gain_ctrl : 3; unsigned unused1 : 1; unsigned vco_rng_ctrl : 3; unsigned unused2 : 1; } b; unsigned long w; } PLL_CPUX_TUN_REG

42) CPUX_AXI_CFG_REG | 0x0500

typedef union cpux_axi_cfg_reg { struct { unsigned factor_m : 2; unsigned unused0 : 6; unsigned cpux_apb_factor_n : 2; unsigned unused1 : 14; unsigned clk_src_sel : 3; unsigned unused2 : 5; } b; unsigned long w; } CPUX_AXI_CFG_REG

43) PSI_AHB1_AHB2_CFG_REG | 0x0510

typedef union psi_ahb1_ahb2_cfg_reg { struct { unsigned factor_m : 2; unsigned unused0 : 6; unsigned factor_n. : 2; unsigned unused1 : 14; unsigned clk_src_sel : 2; unsigned unused2 : 6; } b; unsigned long w; } PSI_AHB1_AHB2_CFG_REG

44) AHB3_CFG_REG | 0x051C

typedef union ahb3_cfg_reg { struct { unsigned factor_m : 2; unsigned unused0 : 6; unsigned factor_n : 2; unsigned unused1 : 14; unsigned clk_src_sel : 2; unsigned unused2 : 6; } b; unsigned long w; } AHB3_CFG_REG

45) APB1_CFG_REG | 0x0520

typedef union apb1_cfg_reg { struct { unsigned factor_m : 2; unsigned unused0 : 6; unsigned factor_n : 2; unsigned unused1 : 14; unsigned clk_src_sel : 2; unsigned unused2 : 6; } b; unsigned long w; } APB1_CFG_REG

46) APB2_CFG_REG | 0x0524

typedef union apb2_cfg_reg { struct { unsigned factor_m : 2; unsigned unused0 : 6; unsigned factor_n : 2; unsigned unused1 : 14; unsigned clk_src_sel : 2; unsigned unused2 : 6; } b; unsigned long w; } APB2_CFG_REG

47) MBUS_CFG_REG | 0x0540

typedef union mbus_cfg_reg { struct { unsigned factor_m : 3; unsigned unused0 : 21; unsigned clk_src_sel. : 2; unsigned unused1 : 4; unsigned mbus_rst. : 1; unsigned clk_gating. : 1; } b; unsigned long w; } MBUS_CFG_REG

48) DE_CLK_REG | 0x0600

typedef union de_clk_reg { struct { unsigned factor_m : 4; unsigned unused0 : 20; unsigned clk_src_sel. : 1; unsigned unused1 : 6; unsigned sclk_gating : 1; } b; unsigned long w; } DE_CLK_REG

49) DE_BGR_REG | 0x060C

typedef union de_bgr_reg { struct { unsigned de_gating : 1; unsigned unused0 : 15; unsigned de_rst : 1; unsigned unused1 : 15; } b; unsigned long w; } DE_BGR_REG

50) DI_CLK_REG | 0x0620

typedef union di_clk_reg { struct { unsigned factor_m : 4; unsigned unused0 : 20; unsigned clk_src_sel. : 1; unsigned unused1 : 6; unsigned sclk_gating : 1; } b; unsigned long w; } DI_CLK_REG

51) DI_BGR_REG | 0x062C

typedef union di_bgr_reg { struct { unsigned di_gating : 1; unsigned unused0 : 15; unsigned di_rst : 1; unsigned unused1 : 15; } b; unsigned long w; } DI_BGR_REG

52) G2D_CLK_REG | 0x0630

typedef union g2d_clk_reg { struct { unsigned factor_m : 4; unsigned unused0 : 20; unsigned clk_src_sel. : 1; unsigned unused1 : 6; unsigned sclk_gating : 1; } b; unsigned long w; } G2D_CLK_REG

53) G2D_BGR_REG | 0x063C

typedef union g2d_bgr_reg { struct { unsigned g2d_gating : 1; unsigned unused0 : 15; unsigned g2d_rst : 1; unsigned unused1 : 15; } b; unsigned long w; } G2D_BGR_REG

54) GPU_CLK0_REG | 0x0670

typedef union gpu_clk0_reg { struct { unsigned factor_m : 2; unsigned unused0 : 22; unsigned clk_src_sel : 1; unsigned unused1 : 6; unsigned sclk_gating : 1; } b; unsigned long w; } GPU_CLK0_REG

55) GPU_CLK1_REG | 0x0674

typedef union gpu_clk1_reg { struct { unsigned factor_m : 2; unsigned unused0 : 29; unsigned pll_peri_bak_clk_gating : 1; } b; unsigned long w; } GPU_CLK1_REG

56) GPU_BGR_REG | 0x067C

typedef union gpu_bgr_reg { struct { unsigned gpu_gating. : 1; unsigned unused0 : 15; unsigned gpu_rst. : 1; unsigned unused1 : 15; } b; unsigned long w; } GPU_BGR_REG

57) CE_CLK_REG | 0x0680

typedef union ce_clk_reg { struct { unsigned factor_m : 4; unsigned unused0 : 4; unsigned factor_n : 2; unsigned unused1 : 14; unsigned clk_src_sel : 1; unsigned unused2 : 6; unsigned sclk_gating : 1; } b; unsigned long w; } CE_CLK_REG

58) CE_BGR_REG | 0x068C

typedef union ce_bgr_reg { struct { unsigned ce_gating : 1; unsigned unused0 : 15; unsigned ce_rst : 1; unsigned unused1 : 15; } b; unsigned long w; } CE_BGR_REG

59) VE_CLK_REG | 0x0690

typedef union ve_clk_reg { struct { unsigned factor_m : 3; unsigned unused0 : 21; unsigned clk_src_sel. : 1; unsigned unused1 : 6; unsigned sclk_gating : 1; } b; unsigned long w; } VE_CLK_REG

60) VE_BGR_REG | 0x069C

typedef union ve_bgr_reg { struct { unsigned ve_gating : 1; unsigned unused0 : 15; unsigned ve_rst : 1; unsigned unused1 : 15; } b; unsigned long w; } VE_BGR_REG

61) DMA_BGR_REG | 0x070C

typedef union dma_bgr_reg { struct { unsigned dma_gating : 1; unsigned unused0 : 15; unsigned dma_rst : 1; unsigned unused1 : 15; } b; unsigned long w; } DMA_BGR_REG

62) HSTIMER_BGR_REG | 0x073C

typedef union hstimer_bgr_reg { struct { unsigned hstimer_gating : 1; unsigned unused0 : 15; unsigned hstimer_rst : 1; unsigned unused1 : 15; } b; unsigned long w; } HSTIMER_BGR_REG

63) AVS_CLK_REG | 0x0740

typedef union avs_clk_reg { struct { unsigned unused0 : 31; unsigned sclk_gating : 1; } b; unsigned long w; } AVS_CLK_REG

64) DBGSYS_BGR_REG | 0x078C

typedef union dbgsys_bgr_reg { struct { unsigned dbgsys_gating : 1; unsigned unused0 : 15; unsigned dbgsys_rst : 1; unsigned unused1 : 15; } b; unsigned long w; } DBGSYS_BGR_REG

65) PSI_BGR_REG | 0x079C

typedef union psi_bgr_reg { struct { unsigned psi_gating : 1; unsigned unused0 : 15; unsigned psi_rst : 1; unsigned unused1 : 15; } b; unsigned long w; } PSI_BGR_REG

66) PWM_BGR_REG | 0x07AC

typedef union pwm_bgr_reg { struct { unsigned pwm_gating : 1; unsigned unused0 : 15; unsigned pwm_rst : 1; unsigned unused1 : 15; } b; unsigned long w; } PWM_BGR_REG

67) IOMMU_BGR_REG | 0x07BC

typedef union iommu_bgr_reg { struct { unsigned iommu_gating. : 1; unsigned unused0 : 31; } b; unsigned long w; } IOMMU_BGR_REG

68) DRAM_CLK_REG | 0x0800

typedef union dram_clk_reg { struct { unsigned factor_m : 2; unsigned unused0 : 22; unsigned clk_src_sel : 2; unsigned unused1 : 4; unsigned module_rst : 1; unsigned unused2 : 1; } b; unsigned long w; } DRAM_CLK_REG

69) MBUS_MAT_CLK_GATING_REG | 0x0804

typedef union mbus_mat_clk_gating_reg { struct { unsigned dma_mclk_gating : 1; unsigned ve_mclk_gating : 1; unsigned ce_mclk_gating : 1; unsigned ts0_mclk_gating : 1; unsigned unused0 : 1; unsigned nand0_mclk_gating : 1; unsigned unused1 : 2; unsigned reserv : 1; unsigned unused2 : 1; unsigned g2d_mclk_gating : 1; unsigned unused3 : 21; } b; unsigned long w; } MBUS_MAT_CLK_GATING_REG

70) DRAM_BGR_REG | 0x080C

typedef union dram_bgr_reg { struct { unsigned dram_gating : 1; unsigned unused0 : 15; unsigned dram_rst : 1; unsigned unused1 : 15; } b; unsigned long w; } DRAM_BGR_REG

71) NAND0_0_CLK_REG | 0x0810

typedef union nand0_0_clk_reg { struct { unsigned factor_m : 4; unsigned unused0 : 4; unsigned factor_n : 2; unsigned unused1 : 14; unsigned clk_src_sel : 3; unsigned unused2 : 4; unsigned sclk_gating : 1; } b; unsigned long w; } NAND0_0_CLK_REG

72) NAND0_1_CLK_REG | 0x0814

typedef union nand0_1_clk_reg { struct { unsigned factor_m : 4; unsigned unused0 : 4; unsigned factor_n : 2; unsigned unused1 : 14; unsigned clk_src_sel : 3; unsigned unused2 : 4; unsigned sclk_gating : 1; } b; unsigned long w; } NAND0_1_CLK_REG

73) NAND_BGR_REG | 0x082C

typedef union nand_bgr_reg { struct { unsigned nand0_gating : 1; unsigned unused0 : 15; unsigned nand0_rst : 1; unsigned unused1 : 15; } b; unsigned long w; } NAND_BGR_REG

74) SMHC0_CLK_REG | 0x0830

typedef union smhc0_clk_reg { struct { unsigned factor_m : 4; unsigned unused0 : 4; unsigned factor_n : 2; unsigned unused1 : 14; unsigned clk_src_sel : 2; unsigned unused2 : 5; unsigned sclk_gating : 1; } b; unsigned long w; } SMHC0_CLK_REG

75) SMHC1_CLK_REG | 0x0834

typedef union smhc1_clk_reg { struct { unsigned factor_m : 4; unsigned unused0 : 4; unsigned factor_n : 2; unsigned unused1 : 14; unsigned clk_src_sel : 2; unsigned unused2 : 5; unsigned sclk_gating : 1; } b; unsigned long w; } SMHC1_CLK_REG

76) SMHC2_CLK_REG | 0x0838

typedef union smhc2_clk_reg { struct { unsigned factor_m : 4; unsigned unused0 : 4; unsigned factor_n : 2; unsigned unused1 : 14; unsigned clk_src_sel : 2; unsigned unused2 : 5; unsigned sclk_gating : 1; } b; unsigned long w; } SMHC2_CLK_REG

77) SMHC_BGR_REG | 0x084C

typedef union smhc_bgr_reg { struct { unsigned smhc0_gating : 1; unsigned smhc1_gating : 1; unsigned smhc2_gating : 1; unsigned unused0 : 13; unsigned smhc0_rst : 1; unsigned smhc1_rst : 1; unsigned smhc2_rst : 1; unsigned unused1 : 13; } b; unsigned long w; } SMHC_BGR_REG

78) UART_BGR_REG | 0x090C

typedef union uart_bgr_reg { struct { unsigned uart0_gating : 1; unsigned uart1_gating : 1; unsigned uart2_gating : 1; unsigned uart3_gating : 1; unsigned uart4_gating : 1; unsigned uart5_gating : 1; unsigned unused0 : 10; unsigned uart0_rst : 1; unsigned uart1_rst : 1; unsigned uart2_rst : 1; unsigned uart3_rst : 1; unsigned uart4_rst : 1; unsigned uart5_rst : 1; unsigned unused1 : 10; } b; unsigned long w; } UART_BGR_REG

79) TWI_BGR_REG | 0x091C

typedef union twi_bgr_reg { struct { unsigned twi0_gating : 1; unsigned twi1_gating : 1; unsigned twi2_gating : 1; unsigned twi3_gating : 1; unsigned twi4_gating : 1; unsigned unused0 : 11; unsigned twi0_rst : 1; unsigned twi1_rst : 1; unsigned twi2_rst : 1; unsigned twi3_rst : 1; unsigned twi4_rst : 1; unsigned unused1 : 11; } b; unsigned long w; } TWI_BGR_REG

80) SPI0_CLK_REG | 0x0940

typedef union spi0_clk_reg { struct { unsigned factor_m : 4; unsigned unused0 : 4; unsigned factor_n : 2; unsigned unused1 : 14; unsigned clk_src_sel : 3; unsigned unused2 : 4; unsigned sclk_gating : 1; } b; unsigned long w; } SPI0_CLK_REG

81) SPI1_CLK_REG | 0x0944

typedef union spi1_clk_reg { struct { unsigned factor_m : 4; unsigned unused0 : 4; unsigned factor_n : 2; unsigned unused1 : 14; unsigned clk_src_sel : 3; unsigned unused2 : 4; unsigned sclk_gating : 1; } b; unsigned long w; } SPI1_CLK_REG

82) SPI_BGR_REG | 0x096C

typedef union spi_bgr_reg { struct { unsigned spi0_gating : 1; unsigned spi1_gating : 1; unsigned unused0 : 14; unsigned spi0_rst : 1; unsigned spi1_rst : 1; unsigned unused1 : 14; } b; unsigned long w; } SPI_BGR_REG

83) EPHY_25M_CLK_REG | 0x0970

typedef union ephy_25m_clk_reg { struct { unsigned unused0 : 30; unsigned pll_peri0_gating : 1; unsigned sclk_gating : 1; } b; unsigned long w; } EPHY_25M_CLK_REG

84) EMAC_BGR_REG | 0x097C

typedef union emac_bgr_reg { struct { unsigned emac0_gating : 1; unsigned emac1_gating : 1; unsigned unused0 : 14; unsigned emac0_rst : 1; unsigned emac1_rst : 1; unsigned unused1 : 14; } b; unsigned long w; } EMAC_BGR_REG

85) TS_CLK_REG | 0x09B0

typedef union ts_clk_reg { struct { unsigned factor_m : 4; unsigned unused0 : 4; unsigned factor_n : 2; unsigned unused1 : 14; unsigned clk_src_sel : 1; unsigned unused2 : 6; unsigned sclk_gating : 1; } b; unsigned long w; } TS_CLK_REG

86) TS_BGR_REG | 0x09BC

typedef union ts_bgr_reg { struct { unsigned ts_gating : 1; unsigned unused0 : 15; unsigned ts_rst : 1; unsigned unused1 : 15; } b; unsigned long w; } TS_BGR_REG

87) THS_BGR_REG | 0x09FC

typedef union ths_bgr_reg { struct { unsigned ths_gating : 1; unsigned unused0 : 15; unsigned ths_rst : 1; unsigned unused1 : 15; } b; unsigned long w; } THS_BGR_REG

88) OWA_CLK_REG | 0x0A20

typedef union owa_clk_reg { struct { unsigned unused0 : 8; unsigned factor_n : 2; unsigned unused1 : 14; unsigned clk_src_sel : 2; unsigned unused2 : 5; unsigned sclk_gating : 1; } b; unsigned long w; } OWA_CLK_REG

89) OWA_BGR_REG | 0x0A2C

typedef union owa_bgr_reg { struct { unsigned owa_gating. : 1; unsigned unused0 : 15; unsigned owa_rst : 1; unsigned unused1 : 15; } b; unsigned long w; } OWA_BGR_REG

90) DMIC_CLK_REG | 0x0A40

typedef union dmic_clk_reg { struct { unsigned unused0 : 8; unsigned factor_n : 2; unsigned unused1 : 14; unsigned clk_src_sel : 2; unsigned unused2 : 5; unsigned sclk_gating : 1; } b; unsigned long w; } DMIC_CLK_REG

91) DMIC_BGR_REG | 0x0A4C

typedef union dmic_bgr_reg { struct { unsigned dmic_gating. : 1; unsigned unused0 : 15; unsigned dmic_rst : 1; unsigned unused1 : 15; } b; unsigned long w; } DMIC_BGR_REG

92) AUDIO_CODEC_1X_CLK_REG | 0x0A50

typedef union audio_codec_1x_clk_reg { struct { unsigned factor_m : 4; unsigned unused0 : 20; unsigned clk_src_sel : 2; unsigned unused1 : 5; unsigned sclk_gating : 1; } b; unsigned long w; } AUDIO_CODEC_1X_CLK_REG

93) AUDIO_CODEC_4X_CLK_REG | 0x0A54

typedef union audio_codec_4x_clk_reg { struct { unsigned factor_m : 4; unsigned unused0 : 20; unsigned clk_src_sel : 2; unsigned unused1 : 5; unsigned sclk_gating : 1; } b; unsigned long w; } AUDIO_CODEC_4X_CLK_REG

94) AUDIO_CODEC_BGR_REG | 0x0A5C

typedef union audio_codec_bgr_reg { struct { unsigned audio_codec_gating : 1; unsigned unused0 : 15; unsigned audio_codec_rst : 1; unsigned unused1 : 15; } b; unsigned long w; } AUDIO_CODEC_BGR_REG

95) AUDIO_HUB_CLK_REG | 0x0A60

typedef union audio_hub_clk_reg { struct { unsigned unused0 : 8; unsigned factor_n : 2; unsigned unused1 : 14; unsigned clk_src_sel : 2; unsigned unused2 : 5; unsigned sclk_gating : 1; } b; unsigned long w; } AUDIO_HUB_CLK_REG

96) AUDIO_HUB_BGR_REG | 0x0A6C

typedef union audio_hub_bgr_reg { struct { unsigned audio_hub_gating : 1; unsigned unused0 : 15; unsigned audio_hub_rst : 1; unsigned unused1 : 15; } b; unsigned long w; } AUDIO_HUB_BGR_REG

97) USB0_CLK_REG | 0x0A70

typedef union usb0_clk_reg { struct { unsigned unused0 : 24; unsigned ohci0_12m_src_sel : 2; unsigned unused1 : 3; unsigned sclk_gating_usbphy0 : 1; unsigned usbphy0_rst : 1; unsigned sclk_gating_ohci0 : 1; } b; unsigned long w; } USB0_CLK_REG

98) USB1_CLK_REG | 0x0A74

typedef union usb1_clk_reg { struct { unsigned unused0 : 24; unsigned ohci1_12m_src_sel : 2; unsigned unused1 : 3; unsigned sclk_gating_usbphy1 : 1; unsigned usbphy1_rst : 1; unsigned sclk_gating_ohci1 : 1; } b; unsigned long w; } USB1_CLK_REG

99) USB2_CLK_REG | 0x0A78

typedef union usb2_clk_reg { struct { unsigned unused0 : 24; unsigned ohci2_12m_src_sel : 2; unsigned unused1 : 3; unsigned sclk_gating_usbphy2 : 1; unsigned usbphy2_rst : 1; unsigned sclk_gating_ohci2 : 1; } b; unsigned long w; } USB2_CLK_REG

100) USB_BGR_REG | 0x0A8C

typedef union usb_bgr_reg { struct { unsigned usbohci0_gating : 1; unsigned usbohci1_gating : 1; unsigned usbohci2_gating : 1; unsigned usbohci3_gating : 1; unsigned usbehci0_gating : 1; unsigned usbehci1_gating : 1; unsigned usbehci2_gating : 1; unsigned usbehci3_gating : 1; unsigned usbotg_gating : 1; unsigned unused0 : 7; unsigned usbohci0_rst : 1; unsigned usbohci1_rst. : 1; unsigned usbohci2_rst. : 1; unsigned usbohci3_rst. : 1; unsigned usbehci0_rst : 1; unsigned usbehci1_rst : 1; unsigned usbehci2_rst : 1; unsigned usbehci3_rst : 1; unsigned usbotg_rst : 1; unsigned unused1 : 7; } b; unsigned long w; } USB_BGR_REG

101) HDMI0_CLK_REG | 0x0B00

typedef union hdmi0_clk_reg { struct { unsigned factor_m : 4; unsigned unused0 : 20; unsigned clk_src_sel : 2; unsigned unused1 : 5; unsigned sclk_gating : 1; } b; unsigned long w; } HDMI0_CLK_REG

102) HDMI0_SLOW_CLK_REG | 0x0B04

typedef union hdmi0_slow_clk_reg { struct { unsigned unused0 : 31; unsigned sclk_gating : 1; } b; unsigned long w; } HDMI0_SLOW_CLK_REG

103) HDMI_CEC_CLK_REG | 0x0B10

typedef union hdmi_cec_clk_reg { struct { unsigned unused0 : 24; unsigned clk_src_sel : 2; unsigned unused1 : 4; unsigned pll_peri_gating : 1; unsigned sclk_gating : 1; } b; unsigned long w; } HDMI_CEC_CLK_REG

104) HDMI_BGR_REG | 0x0B1C

typedef union hdmi_bgr_reg { struct { unsigned hdmi0_gating : 1; unsigned unused0 : 15; unsigned hdmi0_main_rst : 1; unsigned hdmi0_sub_rst : 1; unsigned unused1 : 14; } b; unsigned long w; } HDMI_BGR_REG

105) DISPLAY_IF_TOP_BGR_REG | 0x0B5C

typedef union display_if_top_bgr_reg { struct { unsigned display_if_top_gating : 1; unsigned unused0 : 15; unsigned display_if_top_rst : 1; unsigned unused1 : 15; } b; unsigned long w; } DISPLAY_IF_TOP_BGR_REG

106) TCON_TV0_CLK_REG | 0x0B80

typedef union tcon_tv0_clk_reg { struct { unsigned factor_m : 4; unsigned unused0 : 4; unsigned factor_n : 2; unsigned unused1 : 14; unsigned clk_src_sel : 3; unsigned unused2 : 4; unsigned sclk_gating : 1; } b; unsigned long w; } TCON_TV0_CLK_REG

107) TCON_TV1_CLK_REG | 0x0B80

typedef union tcon_tv1_clk_reg { struct { unsigned factor_m : 4; unsigned unused0 : 4; unsigned factor_n : 2; unsigned unused1 : 14; unsigned clk_src_sel : 3; unsigned unused2 : 4; unsigned sclk_gating : 1; } b; unsigned long w; } TCON_TV1_CLK_REG

108) TCON_TV_BGR_REG | 0x0B9C

typedef union tcon_tv_bgr_reg { struct { unsigned tcon_tv0_gating : 1; unsigned tcon_tv1_gating : 1; unsigned unused0 : 14; unsigned tcon_tv0_rst : 1; unsigned tcon_tv1_rst : 1; unsigned unused1 : 14; } b; unsigned long w; } TCON_TV_BGR_REG

109) TVE0_CLK_REG | 0x0BB0

typedef union tve0_clk_reg { struct { unsigned factor_m : 4; unsigned unused0 : 4; unsigned factor_n : 2; unsigned unused1 : 14; unsigned clk_src_sel : 3; unsigned unused2 : 4; unsigned sclk_gating : 1; } b; unsigned long w; } TVE0_CLK_REG

110) TVE_BGR_REG | 0x0BBC

typedef union tve_bgr_reg { struct { unsigned tve_top_gating : 1; unsigned tve0_gating : 1; unsigned unused0 : 14; unsigned tve_top_rst : 1; unsigned tve0_rst : 1; unsigned unused1 : 14; } b; unsigned long w; } TVE_BGR_REG

111) HDMI_HDCP_CLK_REG | 0x0C40

typedef union hdmi_hdcp_clk_reg { struct { unsigned factor_m : 4; unsigned unused0 : 20; unsigned clk_src_sel : 2; unsigned unused1 : 5; unsigned sclk_gating : 1; } b; unsigned long w; } HDMI_HDCP_CLK_REG

112) HDMI_HDCP_BGR_REG | 0x0C4C

typedef union hdmi_hdcp_bgr_reg { struct { unsigned hdmi_hdcp_gating : 1; unsigned unused0 : 15; unsigned hdmi_hdcp_rst : 1; unsigned unused1 : 15; } b; unsigned long w; } HDMI_HDCP_BGR_REG

113) CCU_SEC_SWITCH_REG | 0x0F00

typedef union ccu_sec_switch_reg { struct { unsigned pll_sec : 1; unsigned bus_sec : 1; unsigned mbus_sec : 1; unsigned unused0 : 29; } b; unsigned long w; } CCU_SEC_SWITCH_REG

114) PLL_LOCK_DBG_CTRL_REG | 0x0F04

typedef union pll_lock_dbg_ctrl_reg { struct { unsigned unused0 : 16; unsigned lock_level : 1; unsigned unlock_level : 2; unsigned unused1 : 1; unsigned dbg_sel : 5; unsigned unused2 : 6; unsigned dbg_en : 1; } b; unsigned long w; } PLL_LOCK_DBG_CTRL_REG

115) FRE_DET_CTRL_REG | 0x0F08

typedef union fre_det_ctrl_reg { struct { unsigned fre_det_fun_en : 1; unsigned fre_det_irq_en : 1; unsigned unused0 : 2; unsigned detect_time : 5; unsigned unused1 : 22; unsigned error_flag : 1; } b; unsigned long w; } FRE_DET_CTRL_REG

116) FRE_UP_LIM_REG | 0x0F0C

typedef union fre_up_lim_reg { struct { unsigned fre_up_lim : 32; } b; unsigned long w; } FRE_UP_LIM_REG

117) FRE_DOWN_LIM_REG | 0x0F10

typedef union fre_down_lim_reg { struct { unsigned fre_down_lim : 32; } b; unsigned long w; } FRE_DOWN_LIM_REG

118) 24M_27M_CLK_OUTPUT_REG | 0x0F20

typedef union 24m_27m_clk_output_reg { struct { unsigned div_sel : 2; unsigned unused0 : 28; unsigned 24m_27m_sel : 1; unsigned 27m_clk_output_en : 1; } b; unsigned long w; } 24M_27M_CLK_OUTPUT_REG

119) PLL_VIDEO2_CTRL_REG | 0x0050

typedef union pll_video2_ctrl_reg { struct { unsigned pll_output_div_d : 1; unsigned pll_input_div_m : 1; unsigned unused0 : 6; unsigned pll_factor_n : 8; unsigned unused1 : 8; unsigned pll_sdm_enable : 1; unsigned unused2 : 2; unsigned pll_output_enable : 1; unsigned lock : 1; unsigned lock_enable : 1; unsigned unused3 : 1; unsigned pll_enable : 1; } b; unsigned long w; } PLL_VIDEO2_CTRL_REG

120) PLL_VIDEO2_PAT0_CTRL_REG | 0x0150

typedef union pll_video2_pat0_ctrl_reg { struct { unsigned wave_bot : 17; unsigned freq : 2; unsigned sdm_clk_sel : 1; unsigned wave_step : 9; unsigned spr_freq_mode : 2; unsigned sig_delt_pat_en : 1; } b; unsigned long w; } PLL_VIDEO2_PAT0_CTRL_REG

121) PLL_VIDEO2_PAT1_CTRL_REG | 0x0154

typedef union pll_video2_pat1_ctrl_reg { struct { unsigned frac_in : 17; unsigned unused0 : 3; unsigned frac_en : 1; unsigned unused1 : 3; unsigned dither_en : 1; unsigned unused2 : 6; unsigned hershey_en : 1; } b; unsigned long w; } PLL_VIDEO2_PAT1_CTRL_REG

122) PLL_VIDEO2_BIAS_REG | 0x0350

typedef union pll_video2_bias_reg { struct { unsigned unused0 : 16; unsigned pll_bias_ctrl : 5; unsigned unused1 : 11; } b; unsigned long w; } PLL_VIDEO2_BIAS_REG

123) USB3_CLK_REG | 0x0A7C

typedef union usb3_clk_reg { struct { unsigned unused0 : 24; unsigned ohci3_12m_src_sel : 2; unsigned unused1 : 3; unsigned sclk_gating_usbphy3 : 1; unsigned usbphy3_rst : 1; unsigned sclk_gating_ohci3 : 1; } b; unsigned long w; } USB3_CLK_REG

124) LRADC_BGR_REG | 0x0A9C

typedef union lradc_bgr_reg { struct { unsigned lradc_gating : 1; unsigned unused0 : 15; unsigned lradc_rst : 1; unsigned unused1 : 15; } b; unsigned long w; } LRADC_BGR_REG